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authorMichal Krol <[email protected]>2008-08-13 11:19:24 +0200
committerMichal Krol <[email protected]>2008-08-13 11:19:24 +0200
commite7e992b12ab3717eadaf055fe2fab88c3be8a092 (patch)
tree5f71469aa7e9433decbf5627fb5a7c4b66f7ff6a /src
parentdb38708c43d7e9bbc744893ad2e9c2a77e9ec15c (diff)
mesa: KIL -> KIL, KIL_NV -> KILP.
Diffstat (limited to 'src')
-rw-r--r--src/mesa/state_tracker/st_mesa_to_tgsi.c8
1 files changed, 4 insertions, 4 deletions
diff --git a/src/mesa/state_tracker/st_mesa_to_tgsi.c b/src/mesa/state_tracker/st_mesa_to_tgsi.c
index 6565107b107..198d406b593 100644
--- a/src/mesa/state_tracker/st_mesa_to_tgsi.c
+++ b/src/mesa/state_tracker/st_mesa_to_tgsi.c
@@ -376,13 +376,13 @@ compile_instruction(
fullinst->Instruction.Opcode = TGSI_OPCODE_INT;
break;
case OPCODE_KIL:
- /* predicated w/ a register */
- fullinst->Instruction.Opcode = TGSI_OPCODE_KILP;
+ /* conditional */
+ fullinst->Instruction.Opcode = TGSI_OPCODE_KIL;
break;
case OPCODE_KIL_NV:
- /* unpredicated */
+ /* predicated */
assert(inst->DstReg.CondMask == COND_TR);
- fullinst->Instruction.Opcode = TGSI_OPCODE_KIL;
+ fullinst->Instruction.Opcode = TGSI_OPCODE_KILP;
break;
case OPCODE_LG2:
fullinst->Instruction.Opcode = TGSI_OPCODE_LG2;