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authorIlia Mirkin <[email protected]>2014-09-16 02:09:49 -0400
committerRob Clark <[email protected]>2014-09-22 22:06:34 -0400
commit9a3dcf21d7ba116d670aad428ccce415eebdf645 (patch)
tree963cbc41865505bd3889abe6bc1a03ed77e61f65 /src
parent53678f5e6b4964136c04694aea771b1d433c8fab (diff)
freedreno/ir3: fix TXB/TXL to actually pull the bias/lod argument
Previously we would get a potentially computed post-swizzle coord based on the texture target info, which would not include the bias/lod in the last argument. The second argument does not have to be adjacent, so adjusting the order array did not make sense. Signed-off-by: Ilia Mirkin <[email protected]> Signed-off-by: Rob Clark <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/gallium/drivers/freedreno/ir3/ir3_compiler.c5
1 files changed, 4 insertions, 1 deletions
diff --git a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
index c0ef6b20cd4..d5d7502d2e8 100644
--- a/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
+++ b/src/gallium/drivers/freedreno/ir3/ir3_compiler.c
@@ -1248,6 +1248,7 @@ trans_samp(const struct instr_translater *t,
{
struct ir3_instruction *instr;
struct tgsi_dst_register *dst = &inst->Dst[0].Register;
+ struct tgsi_src_register *orig = &inst->Src[0].Register;
struct tgsi_src_register *coord;
struct tgsi_src_register *samp = &inst->Src[1].Register;
struct tex_info tinf;
@@ -1255,6 +1256,8 @@ trans_samp(const struct instr_translater *t,
memset(&tinf, 0, sizeof(tinf));
fill_tex_info(ctx, inst, &tinf);
coord = get_tex_coord(ctx, inst, &tinf);
+ if (tinf.args > 1 && is_rel_or_const(orig))
+ orig = get_unconst(ctx, orig);
instr = instr_create(ctx, 5, t->opc);
instr->cat5.type = get_ftype(ctx);
@@ -1266,7 +1269,7 @@ trans_samp(const struct instr_translater *t,
add_src_reg_wrmask(ctx, instr, coord, coord->SwizzleX, tinf.src_wrmask);
if (tinf.args > 1)
- add_src_reg_wrmask(ctx, instr, coord, coord->SwizzleW, 0x1);
+ add_src_reg_wrmask(ctx, instr, orig, orig->SwizzleW, 0x1);
}
/* DDX/DDY */