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authorEric Anholt <eric@anholt.net>2011-11-22 16:26:55 -0800
committerEric Anholt <eric@anholt.net>2011-11-29 11:18:23 -0800
commit09e67706e9a74600e16fe012ecfd192b0d31960a (patch)
treebe6c2043ab84b4d6a13c157b2eb7ce9ac3ecca31 /src
parente6c314f7d2ed99714376fec6b7509a55535fa3ff (diff)
i965: Don't depth test the fake depthbuffer when one isn't present.
For the non-separate-stencil-only case, we've been using a NULL surface for depth, so we didn't have to care. However, to support separate stencil with no depthbuffer, we have to make the depth surface non-NULL or the stencil test always fails thanks to separate stencil inheriting the surface type of depth. Fixes hiz-depth-stencil-test-d0-s8. Reviewed-by: Chad Versace <chad.versace@linux.intel.com>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/gen6_depthstencil.c7
1 files changed, 6 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_depthstencil.c b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
index eec1bf69015..c601a8fb13e 100644
--- a/src/mesa/drivers/dri/i965/gen6_depthstencil.c
+++ b/src/mesa/drivers/dri/i965/gen6_depthstencil.c
@@ -25,6 +25,7 @@
*
*/
+#include "intel_fbo.h"
#include "brw_context.h"
#include "brw_state.h"
@@ -33,6 +34,10 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
{
struct gl_context *ctx = &brw->intel.ctx;
struct gen6_depth_stencil_state *ds;
+ struct intel_renderbuffer *depth_irb;
+
+ /* _NEW_BUFFERS */
+ depth_irb = intel_get_renderbuffer(ctx->DrawBuffer, BUFFER_DEPTH);
ds = brw_state_batch(brw, AUB_TRACE_DEPTH_STENCIL_STATE,
sizeof(*ds), 64,
@@ -77,7 +82,7 @@ gen6_upload_depth_stencil_state(struct brw_context *brw)
}
/* _NEW_DEPTH */
- if (ctx->Depth.Test || brw->hiz.op) {
+ if ((ctx->Depth.Test || brw->hiz.op) && depth_irb) {
assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_RESOLVE || ctx->Depth.Test);
assert(brw->hiz.op != BRW_HIZ_OP_HIZ_RESOLVE || !ctx->Depth.Test);
assert(brw->hiz.op != BRW_HIZ_OP_DEPTH_CLEAR || !ctx->Depth.Test);