diff options
author | Marek Olšák <[email protected]> | 2015-07-16 19:55:42 +0200 |
---|---|---|
committer | Marek Olšák <[email protected]> | 2015-08-02 22:03:33 +0200 |
commit | 08fd736a45c98bd0acd96dfc1a61e6a695d2703c (patch) | |
tree | 1de58c3a2b11cb03b85eb1b4eed3b8c656b14b81 /src | |
parent | 4d7e0fa8c731776ad5d630f37b36c535f1907371 (diff) |
radeonsi: flush if the memory usage for an IB is too high
Picked from the amdgpu branch.
Reviewed-by: Michel Dänzer <[email protected]>
Reviewed-by: Christian König <[email protected]>
Diffstat (limited to 'src')
-rw-r--r-- | src/gallium/drivers/radeonsi/si_hw_context.c | 13 | ||||
-rw-r--r-- | src/gallium/drivers/radeonsi/si_state.c | 4 |
2 files changed, 17 insertions, 0 deletions
diff --git a/src/gallium/drivers/radeonsi/si_hw_context.c b/src/gallium/drivers/radeonsi/si_hw_context.c index 1aef37b18b5..581b130caec 100644 --- a/src/gallium/drivers/radeonsi/si_hw_context.c +++ b/src/gallium/drivers/radeonsi/si_hw_context.c @@ -32,6 +32,19 @@ void si_need_cs_space(struct si_context *ctx, unsigned num_dw, { int i; + /* There are two memory usage counters in the winsys for all buffers + * that have been added (cs_add_reloc) and two counters in the pipe + * driver for those that haven't been added yet. + * */ + if (!ctx->b.ws->cs_memory_below_limit(ctx->b.rings.gfx.cs, ctx->b.vram, ctx->b.gtt)) { + ctx->b.gtt = 0; + ctx->b.vram = 0; + ctx->b.rings.gfx.flush(ctx, RADEON_FLUSH_ASYNC, NULL); + return; + } + ctx->b.gtt = 0; + ctx->b.vram = 0; + /* The number of dwords we already used in the CS so far. */ num_dw += ctx->b.rings.gfx.cs->cdw; diff --git a/src/gallium/drivers/radeonsi/si_state.c b/src/gallium/drivers/radeonsi/si_state.c index d0269f0fe86..867dbc68633 100644 --- a/src/gallium/drivers/radeonsi/si_state.c +++ b/src/gallium/drivers/radeonsi/si_state.c @@ -2059,6 +2059,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, if (rtex->fmask.size && rtex->cmask.size) { sctx->framebuffer.compressed_cb_mask |= 1 << i; } + r600_context_add_resource_size(ctx, surf->base.texture); } /* Set the 16BPC export for possible dual-src blending. */ if (i == 1 && surf && surf->export_16bpc) { @@ -2073,6 +2074,7 @@ static void si_set_framebuffer_state(struct pipe_context *ctx, if (!surf->depth_initialized) { si_init_depth_surface(sctx, surf); } + r600_context_add_resource_size(ctx, surf->base.texture); } si_update_fb_rs_state(sctx); @@ -2815,6 +2817,7 @@ static void si_set_vertex_buffers(struct pipe_context *ctx, pipe_resource_reference(&dsti->buffer, src->buffer); dsti->buffer_offset = src->buffer_offset; dsti->stride = src->stride; + r600_context_add_resource_size(ctx, src->buffer); } } else { for (i = 0; i < count; i++) { @@ -2832,6 +2835,7 @@ static void si_set_index_buffer(struct pipe_context *ctx, if (ib) { pipe_resource_reference(&sctx->index_buffer.buffer, ib->buffer); memcpy(&sctx->index_buffer, ib, sizeof(*ib)); + r600_context_add_resource_size(ctx, ib->buffer); } else { pipe_resource_reference(&sctx->index_buffer.buffer, NULL); } |