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authorKenneth Graunke <[email protected]>2014-01-22 16:48:03 -0800
committerKenneth Graunke <[email protected]>2014-01-25 19:20:17 -0800
commit07149f0252c52b4ac58b6df4e307fd786b49b490 (patch)
tree6297c643f9e7af9347f63403991a047b6ae529c3 /src
parenta487b4d0e3dfdf21d9604d4e36c65c5113c4ce7a (diff)
i965: Don't store qpitch / 4 as mt->qpitch for compressed surfaces.
Broadwell requires software to specify QPitch in a bunch of packets, so we decided to store it in the miptree. However, when I did that refactoring, I missed a subtlety: the hardware expects QPitch to be "in units of rows in the uncompressed surface". This is the value we originally compute. However, for compressed surfaces, we then divided it by 4 (the block height), to obtain the physical layout. This is no longer the QPitch Broadwell expects. So, store the original undivided value in mt->qpitch, but continue to use the divided value in brw_miptree_layout_texture_array(). For non-Broadwell platforms, this should have no impact at all. Helps fix Piglit's "getteximage-targets S3TC CUBE" test on Broadwell. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src')
-rw-r--r--src/mesa/drivers/dri/i965/brw_tex_layout.c8
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.h5
2 files changed, 8 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_tex_layout.c b/src/mesa/drivers/dri/i965/brw_tex_layout.c
index 45aa85471af..f5ea13437ae 100644
--- a/src/mesa/drivers/dri/i965/brw_tex_layout.c
+++ b/src/mesa/drivers/dri/i965/brw_tex_layout.c
@@ -246,17 +246,17 @@ brw_miptree_layout_texture_array(struct brw_context *brw,
mt->qpitch = h0;
else
mt->qpitch = (h0 + h1 + (brw->gen >= 7 ? 12 : 11) * mt->align_h);
- if (mt->compressed)
- mt->qpitch /= 4;
+
+ int physical_qpitch = mt->compressed ? mt->qpitch / 4 : mt->qpitch;
brw_miptree_layout_2d(mt);
for (unsigned level = mt->first_level; level <= mt->last_level; level++) {
for (int q = 0; q < mt->physical_depth0; q++) {
- intel_miptree_set_image_offset(mt, level, q, 0, q * mt->qpitch);
+ intel_miptree_set_image_offset(mt, level, q, 0, q * physical_qpitch);
}
}
- mt->total_height = mt->qpitch * mt->physical_depth0;
+ mt->total_height = physical_qpitch * mt->physical_depth0;
align_cube(mt);
}
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index bc63a249d2a..69d5b0a22c0 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -334,7 +334,10 @@ struct intel_mipmap_tree
bool array_spacing_lod0;
/**
- * The distance in rows between array slices.
+ * The distance in rows between array slices in an uncompressed surface.
+ *
+ * For compressed surfaces, slices are stored closer together physically;
+ * the real distance is (qpitch / block height).
*/
uint32_t qpitch;