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authorSamuel Pitoiset <[email protected]>2018-11-21 11:34:42 +0100
committerSamuel Pitoiset <[email protected]>2018-11-22 08:56:36 +0100
commit4ff4af3d91659285e8a4b198546847d8cc82c381 (patch)
tree8cb33ac8d6f7896f76617e85dda788978ef37f5d /src/vulkan/registry/vk.xml
parent33b2f74e77a33c92c5376a6f11e1a933b8fad4d7 (diff)
radv: remove useless sync after CmdClear{Color,DepthStencil}Image()
'post_flush' is only set to NULL for the normal clear path (ie. only vkCmdClearColorImage() and vkCmdClearDepthStencilImage() are affected commands). Because these two operations have to be externally synchronized with VK_PIPELINE_STAGE_TRANSFER_BIT and VK_ACCESS_TRANSFER_WRITE_BIT, it's useless to set those flags internallY. VK_PIPELINE_STAGE_TRANSFER_BIT will wait for compute to be idle, while VK_ACCESS_TRANSFER_WRITE_BIT will invalidate both L1 vector caches and L2. RADV_CMD_FLAG_WRITEBACK_GLOBAL_L2 will be superseded by RADV_CMD_FLAG_INV_GLOBAL_L2. Signed-off-by: Samuel Pitoiset <[email protected]> Reviewed-by: Bas Nieuwenhuizen <[email protected]>
Diffstat (limited to 'src/vulkan/registry/vk.xml')
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