diff options
| author | Anuj Phogat <[email protected]> | 2018-05-31 15:41:53 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-07-09 15:38:42 -0700 |
| commit | c1d8300117891ec87762caa30d14307622c65bcf (patch) | |
| tree | f3ee9eee84887d1c1dd17125f549b36df509679e /src/util/u_thread.h | |
| parent | 227dabc2664b886e621de03d9ba82073e2fd16aa (diff) | |
anv/icl: Don't set float blend optimization bit in CACHE_MODE_SS
CACHE_MODE_SS is not listed in gfxspecs table for user mode
non-privileged registers. So, making any changes from Mesa
will do nothing. Kernel is already setting this bit in
CACHE_MODE_SS register which is saved/restored to/from
the HW context image.
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/util/u_thread.h')
0 files changed, 0 insertions, 0 deletions