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authorAlyssa Rosenzweig <[email protected]>2019-12-06 12:20:31 -0500
committerAlyssa Rosenzweig <[email protected]>2019-12-12 11:42:07 -0500
commit08b16fb32184eb399ad8007425f35707f99fda1c (patch)
tree51a4ebba3f361c2e90c069bb9c5e45e98f257947 /src/panfrost
parent8e7f2b9ae390f53ac1f761b389682f6950a53c27 (diff)
pan/midgard: Dynamically allocate r26/27 for spills
This allows us to spill two 128-bit values in the same bundle, since we have two registers we can spill with. This improves the register allocation flexibility in programs with heavy spilling, though unfortunately it isn't sufficient (theoretically, 3.5 128-bit values can be spilled from 3 vector units and 2 scalar units). Signed-off-by: Alyssa Rosenzweig <[email protected]>
Diffstat (limited to 'src/panfrost')
-rw-r--r--src/panfrost/midgard/compiler.h13
-rw-r--r--src/panfrost/midgard/midgard_ra.c2
2 files changed, 10 insertions, 5 deletions
diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h
index eb0464e6a49..a6facae4422 100644
--- a/src/panfrost/midgard/compiler.h
+++ b/src/panfrost/midgard/compiler.h
@@ -598,12 +598,17 @@ v_load_store_scratch(
ins.constants[0] = byte;
if (is_store) {
- /* r0 = r26, r1 = r27 */
- assert(srcdest == SSA_FIXED_REGISTER(26) || srcdest == SSA_FIXED_REGISTER(27));
ins.src[0] = srcdest;
- } else {
+
+ /* Ensure we are tightly swizzled so liveness analysis is
+ * correct */
+
+ for (unsigned i = 0; i < 4; ++i) {
+ if (!(mask & (1 << i)))
+ ins.swizzle[0][i] = COMPONENT_X;
+ }
+ } else
ins.dest = srcdest;
- }
return ins;
}
diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c
index 56d1f277d5f..d5cfd6214a2 100644
--- a/src/panfrost/midgard/midgard_ra.c
+++ b/src/panfrost/midgard/midgard_ra.c
@@ -738,7 +738,7 @@ mir_spill_register(
st = v_mov(spill_node, spill_slot);
st.no_spill = true;
} else {
- ins->dest = SSA_FIXED_REGISTER(26);
+ ins->dest = spill_index++;
ins->no_spill = true;
st = v_load_store_scratch(ins->dest, spill_slot, true, ins->mask);
}