diff options
| author | Alyssa Rosenzweig <[email protected]> | 2020-05-11 15:06:53 -0400 |
|---|---|---|
| committer | Marge Bot <[email protected]> | 2020-05-21 17:49:14 +0000 |
| commit | b91d71597e4fba907d27f2a82f070c5a25abde5f (patch) | |
| tree | d826fb8a703ea91b7cf47922760e00623c90c07e /src/panfrost | |
| parent | 1ff2cabe87601d95bf945339ee1b3ea4b4d8bc72 (diff) | |
pan/mdg: Eliminate load_64
It can always be inferred from the types.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5151>
Diffstat (limited to 'src/panfrost')
| -rw-r--r-- | src/panfrost/midgard/compiler.h | 3 | ||||
| -rw-r--r-- | src/panfrost/midgard/midgard_compile.c | 4 | ||||
| -rw-r--r-- | src/panfrost/midgard/midgard_ra.c | 3 | ||||
| -rw-r--r-- | src/panfrost/midgard/mir_promote_uniforms.c | 4 |
4 files changed, 3 insertions, 11 deletions
diff --git a/src/panfrost/midgard/compiler.h b/src/panfrost/midgard/compiler.h index 9de53918644..f9cfcb09fc8 100644 --- a/src/panfrost/midgard/compiler.h +++ b/src/panfrost/midgard/compiler.h @@ -164,9 +164,6 @@ typedef struct midgard_instruction { unsigned nr_dependencies; BITSET_WORD *dependents; - /* For load/store ops.. force 64-bit destination */ - bool load_64; - union { midgard_load_store_word load_store; midgard_vector_alu alu; diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c index 643fe114b0d..1ca2df891f6 100644 --- a/src/panfrost/midgard/midgard_compile.c +++ b/src/panfrost/midgard/midgard_compile.c @@ -1135,9 +1135,7 @@ mir_set_intr_mask(nir_instr *instr, midgard_instruction *ins, bool is_read) /* Once we have the NIR mask, we need to normalize to work in 32-bit space */ unsigned bytemask = pan_to_bytemask(dsize, nir_mask); mir_set_bytemask(ins, bytemask); - - if (dsize == 64) - ins->load_64 = true; + ins->dest_type = nir_type_uint | dsize; } /* Uniforms and UBOs use a shared code path, as uniforms are just (slightly diff --git a/src/panfrost/midgard/midgard_ra.c b/src/panfrost/midgard/midgard_ra.c index 95fd30ec337..faaa41f2839 100644 --- a/src/panfrost/midgard/midgard_ra.c +++ b/src/panfrost/midgard/midgard_ra.c @@ -525,9 +525,6 @@ allocate_registers(compiler_context *ctx, bool *spilled) (size == 64) ? 3 : /* (1 << 3) = 8-byte */ 3; /* 8-bit todo */ - if (ins->type == TAG_LOAD_STORE_4 && ins->load_64) - min_alignment[dest] = 3; - /* We don't have a swizzle for the conditional and we don't * want to muck with the conditional itself, so just force * alignment for now */ diff --git a/src/panfrost/midgard/mir_promote_uniforms.c b/src/panfrost/midgard/mir_promote_uniforms.c index e29de78808d..0cd3a86a9dc 100644 --- a/src/panfrost/midgard/mir_promote_uniforms.c +++ b/src/panfrost/midgard/mir_promote_uniforms.c @@ -192,12 +192,12 @@ midgard_promote_uniforms(compiler_context *ctx) needs_move |= BITSET_TEST(special, ins->dest); if (needs_move) { + unsigned type_size = nir_alu_type_get_type_size(ins->dest_type); midgard_instruction mov = v_mov(promoted, ins->dest); - if (ins->load_64) + if (type_size == 64) mov.alu.reg_mode = midgard_reg_mode_64; - unsigned type_size = nir_alu_type_get_type_size(ins->dest_type); uint16_t rounded = mir_round_bytemask_up(mir_bytemask(ins), type_size); mir_set_bytemask(&mov, rounded); mir_insert_instruction_before(ctx, ins, mov); |