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| author | Alyssa Rosenzweig <[email protected]> | 2019-07-26 11:30:06 -0700 |
|---|---|---|
| committer | Alyssa Rosenzweig <[email protected]> | 2019-07-26 13:38:41 -0700 |
| commit | 9beb3391b5500b17c860356facab9fcff032693b (patch) | |
| tree | 12d01bbbba1c3c80e85e47ff465f8739deb8d4a2 /src/panfrost/midgard/midgard_opt_invert.c | |
| parent | b0626c1f306b8f55911d8926f85dc13c6a327a2f (diff) | |
pan/midgard: Tag SSA/reg
Rather than putting registers after SSA in the MIR indexing, put them
side-by-side, shifted 1, using the bottom bit as the SSA/reg select.
This will allow us to generate SSA temps in the compiler.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Diffstat (limited to 'src/panfrost/midgard/midgard_opt_invert.c')
0 files changed, 0 insertions, 0 deletions