diff options
| author | Alyssa Rosenzweig <[email protected]> | 2020-02-04 09:29:59 -0500 |
|---|---|---|
| committer | Alyssa Rosenzweig <[email protected]> | 2020-02-16 09:16:47 -0500 |
| commit | b2cab6b6db4244cb95abb5bf13734360df8391ea (patch) | |
| tree | ddced03ea28e4b7560d900df3d261f349e18304e /src/panfrost/midgard/midgard_emit.c | |
| parent | a55a2e02a54cadcd9466d02021c2c7a0739c373f (diff) | |
pan/midgard: Fix 32/64 mixed swizzle packing
Occurs in SSBO address computation.
Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/merge_requests/3835>
Diffstat (limited to 'src/panfrost/midgard/midgard_emit.c')
| -rw-r--r-- | src/panfrost/midgard/midgard_emit.c | 9 |
1 files changed, 7 insertions, 2 deletions
diff --git a/src/panfrost/midgard/midgard_emit.c b/src/panfrost/midgard/midgard_emit.c index 1db5980e374..4d58217ceeb 100644 --- a/src/panfrost/midgard/midgard_emit.c +++ b/src/panfrost/midgard/midgard_emit.c @@ -194,8 +194,13 @@ mir_pack_swizzle_alu(midgard_instruction *ins) packed = mir_pack_swizzle_64(ins->swizzle[i], components); if (mode == midgard_reg_mode_32) { - src[i].rep_low |= (ins->swizzle[i][0] >= COMPONENT_Z); - src[i].rep_high |= (ins->swizzle[i][1] >= COMPONENT_Z); + bool lo = ins->swizzle[i][0] >= COMPONENT_Z; + bool hi = ins->swizzle[i][1] >= COMPONENT_Z; + + /* TODO: can we mix halves? */ + assert(lo == hi); + + src[i].rep_low |= lo; } else if (mode < midgard_reg_mode_32) { unreachable("Cannot encode 8/16 swizzle in 64-bit"); } |