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authorIcecream95 <[email protected]>2020-07-06 19:34:49 +1200
committerMarge Bot <[email protected]>2020-07-13 13:35:10 +0000
commit2fa60b70e08fa8aa62bee938bf03018f82710dc2 (patch)
treec591c819c606619480a60fd65848a98074b4ac8c /src/panfrost/midgard/midgard_compile.c
parented4d2739fe078b2d7312bb9bcd38c7a2ea2548d0 (diff)
pan/mdg: Handle non-blend framebuffer lowering
Reviewed-by: Alyssa Rosenzweig <[email protected]> Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/5755>
Diffstat (limited to 'src/panfrost/midgard/midgard_compile.c')
-rw-r--r--src/panfrost/midgard/midgard_compile.c5
1 files changed, 1 insertions, 4 deletions
diff --git a/src/panfrost/midgard/midgard_compile.c b/src/panfrost/midgard/midgard_compile.c
index a432fabc1aa..5d5ffe50ce6 100644
--- a/src/panfrost/midgard/midgard_compile.c
+++ b/src/panfrost/midgard/midgard_compile.c
@@ -1720,7 +1720,6 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
case nir_intrinsic_load_raw_output_pan: {
reg = nir_dest_index(&instr->dest);
- assert(ctx->is_blend);
/* T720 and below use different blend opcodes with slightly
* different semantics than T760 and up */
@@ -1739,7 +1738,6 @@ emit_intrinsic(compiler_context *ctx, nir_intrinsic_instr *instr)
case nir_intrinsic_load_output: {
reg = nir_dest_index(&instr->dest);
- assert(ctx->is_blend);
midgard_instruction ld = m_ld_color_buffer_as_fp16(reg, 0);
@@ -2766,9 +2764,8 @@ midgard_compile_shader_nir(nir_shader *nir, panfrost_program *program, bool is_b
NIR_PASS_V(nir, nir_lower_vars_to_ssa);
unsigned pan_quirks = panfrost_get_quirks(gpu_id);
- if (is_blend)
NIR_PASS_V(nir, pan_lower_framebuffer,
- program->rt_formats, pan_quirks);
+ program->rt_formats, is_blend, pan_quirks);
NIR_PASS_V(nir, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
glsl_type_size, 0);