pan/bi: Move notes on ADD ops to notes file

Again, we'd like to see just the opcode table more clearly.

Signed-off-by: Alyssa Rosenzweig <[email protected]>
Part-of: <https://gitlab.freedesktop.org/mesa/mesa/-/merge_requests/4025>

1 files changed, 80 insertions, 1 deletions

diff --git a/src/panfrost/bifrost/Notes.txt b/src/panfrost/bifrost/Notes.txt
index 53714ac5d6d..5c06edc1c84 100644
--- a/src/panfrost/bifrost/Notes.txt
+++ b/src/panfrost/bifrost/Notes.txt
@@ -1,6 +1,6 @@
 # Notes on opcodes
 
-_Notes by Connor Abbott extracted from the disassembler_
+_Notes mainly by Connor Abbott extracted from the disassembler_
 
 LOG_FREXPM:
 
@@ -99,3 +99,82 @@ LSHIFT_ADD_LOW32:
         // ld_st_op temp, ptr.y, ...
         //
         // Again, the same as the unsigned case except for the offset.
+
+---
+
+ADD ops..
+
+F16_TO_F32.X: // take the low  16 bits, and expand it to a 32-bit float
+F16_TO_F32.Y: // take the high 16 bits, and expand it to a 32-bit float
+
+MOV: 
+        // Logically, this should be SWZ.XY, but that's equivalent to a move, and
+        // this seems to be the canonical way the blob generates a MOV.
+ 
+
+FRCP_FREXPM:
+        // Given a floating point number m * 2^e, returns m ^ 2^{-1}.
+
+FLOG_FREXPE:
+        // From the ARM patent US20160364209A1:
+        // "Decompose v (the input) into numbers x1 and s such that v = x1 * 2^s,
+        // and x1 is a floating point value in a predetermined range where the
+        // value 1 is within the range and not at one extremity of the range (e.g.
+        // choose a range where 1 is towards middle of range)."
+        //
+        // This computes s.
+
+LD_UBO.v4i32
+        // src0 = offset, src1 = binding
+
+FRCP_FAST.f32:
+        // *_FAST does not exist on G71 (added to G51, G72, and everything after)
+
+FRCP_TABLE
+        // Given a floating point number m * 2^e, produces a table-based
+        // approximation of 2/m using the top 17 bits. Includes special cases for
+        // infinity, NaN, and zero, and copies the sign bit.
+
+FRCP_FAST.f16.X
+        // Exists on G71
+
+FRSQ_TABLE:
+        // A similar table for inverse square root, using the high 17 bits of the
+        // mantissa as well as the low bit of the exponent.
+
+FRCP_APPROX:
+        // Used in the argument reduction for log. Given a floating-point number
+        // m * 2^e, uses the top 4 bits of m to produce an approximation to 1/m
+        // with the exponent forced to 0 and only the top 5 bits are nonzero. 0,
+        // infinity, and NaN all return 1.0.
+        // See the ARM patent for more information.
+
+MUX:
+        // For each bit i, return src2[i] ? src0[i] : src1[i]. In other words, this
+        // is the same as (src2 & src0) | (~src2 & src1).
+
+ST_VAR:
+        // store a varying given the address and datatype from LD_VAR_ADDR
+
+LD_VAR_ADDR:
+        // Compute varying address and datatype (for storing in the vertex shader),
+        // and store the vec3 result in the data register. The result is passed as
+        // the 3 normal arguments to ST_VAR.
+
+DISCARD
+        // Conditional discards (discard_if) in NIR. Compares the first two
+        // sources and discards if the result is true
+
+ATEST.f32:
+        // Implements alpha-to-coverage, as well as possibly the late depth and
+        // stencil tests. The first source is the existing sample mask in R60
+        // (possibly modified by gl_SampleMask), and the second source is the alpha
+        // value.  The sample mask is written right away based on the
+        // alpha-to-coverage result using the normal register write mechanism,
+        // since that doesn't need to read from any memory, and then written again
+        // later based on the result of the stencil and depth tests using the
+        // special register.
+
+BLEND:
+        // This takes the sample coverage mask (computed by ATEST above) as a
+        // regular argument, in addition to the vec4 color in the special register.