diff options
| author | Eric Anholt <[email protected]> | 2010-12-08 10:57:22 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2010-12-08 11:14:35 -0800 |
| commit | dba6fde08cca22187ac7bf23462a22147a596683 (patch) | |
| tree | 5a5ee6b7945fd0897a124aebea81f683aea35a18 /src/mesa | |
| parent | 39eaacff14ba2d529a072e737b8fe11f887011ea (diff) | |
i965: Use the new pixel mask location for gen6 ARB_fp KIL instructions.
Fixes:
fp-kil
fp-generic/kil-swizzle.
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_emit.c | 10 |
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_emit.c b/src/mesa/drivers/dri/i965/brw_wm_emit.c index 9822b2cf055..9cb3631236a 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_emit.c +++ b/src/mesa/drivers/dri/i965/brw_wm_emit.c @@ -1305,9 +1305,15 @@ static void emit_kil( struct brw_wm_compile *c, struct brw_reg *arg0) { struct brw_compile *p = &c->func; - struct brw_reg r0uw = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); + struct intel_context *intel = &p->brw->intel; + struct brw_reg pixelmask; GLuint i, j; + if (intel->gen >= 6) + pixelmask = retype(brw_vec1_grf(1, 7), BRW_REGISTER_TYPE_UW); + else + pixelmask = retype(brw_vec1_grf(0, 0), BRW_REGISTER_TYPE_UW); + for (i = 0; i < 4; i++) { /* Check if we've already done the comparison for this reg * -- common when someone does KIL TEMP.wwww. @@ -1323,7 +1329,7 @@ static void emit_kil( struct brw_wm_compile *c, brw_CMP(p, brw_null_reg(), BRW_CONDITIONAL_GE, arg0[i], brw_imm_f(0)); brw_set_predicate_control_flag_value(p, 0xff); brw_set_compression_control(p, BRW_COMPRESSION_NONE); - brw_AND(p, r0uw, brw_flag_reg(), r0uw); + brw_AND(p, pixelmask, brw_flag_reg(), pixelmask); brw_pop_insn_state(p); } } |