i965/vec4: Rename DF to/from F generator opcodes

The opcodes are not specific for conversions to/from float since we need
the same for conversions to/from other 32-bit types. Rename the opcodes
accordingly and change the asserts to check the size of the types involved
instead.

v2:
- Rename to VEC4_OPCODE_TO_DOUBLE and VEC4_OPCODE_FROM_DOUBLE (Matt)

Reviewed-by: Matt Turner <[email protected]>

6 files changed, 20 insertions, 20 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index 4314c4c03e0..3c5c6c484d7 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1098,8 +1098,8 @@ enum opcode {
    VEC4_OPCODE_MOV_BYTES,
    VEC4_OPCODE_PACK_BYTES,
    VEC4_OPCODE_UNPACK_UNIFORM,
-   VEC4_OPCODE_DOUBLE_TO_FLOAT,
-   VEC4_OPCODE_FLOAT_TO_DOUBLE,
+   VEC4_OPCODE_FROM_DOUBLE,
+   VEC4_OPCODE_TO_DOUBLE,
    VEC4_OPCODE_PICK_LOW_32BIT,
    VEC4_OPCODE_PICK_HIGH_32BIT,
    VEC4_OPCODE_SET_LOW_32BIT,
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp
index a919ae4e034..dfc7407ea5b 100644
--- a/src/mesa/drivers/dri/i965/brw_shader.cpp
+++ b/src/mesa/drivers/dri/i965/brw_shader.cpp
@@ -322,10 +322,10 @@ brw_instruction_name(const struct gen_device_info *devinfo, enum opcode op)
       return "pack_bytes";
    case VEC4_OPCODE_UNPACK_UNIFORM:
       return "unpack_uniform";
-   case VEC4_OPCODE_DOUBLE_TO_FLOAT:
-      return "double_to_float";
-   case VEC4_OPCODE_FLOAT_TO_DOUBLE:
-      return "float_to_double";
+   case VEC4_OPCODE_FROM_DOUBLE:
+      return "double_to_single";
+   case VEC4_OPCODE_TO_DOUBLE:
+      return "single_to_double";
    case VEC4_OPCODE_PICK_LOW_32BIT:
       return "pick_low_32bit";
    case VEC4_OPCODE_PICK_HIGH_32BIT:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4.cpp b/src/mesa/drivers/dri/i965/brw_vec4.cpp
index 229a310ec92..6f0f3475223 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4.cpp
@@ -253,8 +253,8 @@ vec4_instruction::can_do_writemask(const struct gen_device_info *devinfo)
 {
    switch (opcode) {
    case SHADER_OPCODE_GEN4_SCRATCH_READ:
-   case VEC4_OPCODE_DOUBLE_TO_FLOAT:
-   case VEC4_OPCODE_FLOAT_TO_DOUBLE:
+   case VEC4_OPCODE_FROM_DOUBLE:
+   case VEC4_OPCODE_TO_DOUBLE:
    case VEC4_OPCODE_PICK_LOW_32BIT:
    case VEC4_OPCODE_PICK_HIGH_32BIT:
    case VEC4_OPCODE_SET_LOW_32BIT:
@@ -513,8 +513,8 @@ vec4_visitor::opt_reduce_swizzle()
          swizzle = brw_swizzle_for_size(2);
          break;
 
-      case VEC4_OPCODE_FLOAT_TO_DOUBLE:
-      case VEC4_OPCODE_DOUBLE_TO_FLOAT:
+      case VEC4_OPCODE_TO_DOUBLE:
+      case VEC4_OPCODE_FROM_DOUBLE:
       case VEC4_OPCODE_PICK_LOW_32BIT:
       case VEC4_OPCODE_PICK_HIGH_32BIT:
       case VEC4_OPCODE_SET_LOW_32BIT:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
index d0045a7f5fa..739f33eed34 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_copy_propagation.cpp
@@ -286,8 +286,8 @@ static bool
 is_align1_opcode(unsigned opcode)
 {
    switch (opcode) {
-   case VEC4_OPCODE_DOUBLE_TO_FLOAT:
-   case VEC4_OPCODE_FLOAT_TO_DOUBLE:
+   case VEC4_OPCODE_FROM_DOUBLE:
+   case VEC4_OPCODE_TO_DOUBLE:
    case VEC4_OPCODE_PICK_LOW_32BIT:
    case VEC4_OPCODE_PICK_HIGH_32BIT:
    case VEC4_OPCODE_SET_LOW_32BIT:
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
index 3039398a64d..6e903e13f3a 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_generator.cpp
@@ -1909,9 +1909,9 @@ generate_code(struct brw_codegen *p,
          break;
       }
 
-      case VEC4_OPCODE_DOUBLE_TO_FLOAT: {
-         assert(src[0].type == BRW_REGISTER_TYPE_DF);
-         assert(dst.type == BRW_REGISTER_TYPE_F);
+      case VEC4_OPCODE_FROM_DOUBLE: {
+         assert(type_sz(src[0].type) == 8);
+         assert(type_sz(dst.type) == 4);
 
          brw_set_default_access_mode(p, BRW_ALIGN_1);
 
@@ -1930,9 +1930,9 @@ generate_code(struct brw_codegen *p,
          break;
       }
 
-      case VEC4_OPCODE_FLOAT_TO_DOUBLE: {
-         assert(src[0].type == BRW_REGISTER_TYPE_F);
-         assert(dst.type == BRW_REGISTER_TYPE_DF);
+      case VEC4_OPCODE_TO_DOUBLE: {
+         assert(type_sz(src[0].type) == 4);
+         assert(type_sz(dst.type) == 8);
 
          brw_set_default_access_mode(p, BRW_ALIGN_1);
 
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
index 3611f8c7323..78f5218b45f 100644
--- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
+++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp
@@ -1116,7 +1116,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
 
       dst_reg temp2 = dst_reg(this, glsl_type::dvec4_type);
       temp2 = retype(temp2, BRW_REGISTER_TYPE_F);
-      emit(VEC4_OPCODE_DOUBLE_TO_FLOAT, temp2, src_reg(temp))
+      emit(VEC4_OPCODE_FROM_DOUBLE, temp2, src_reg(temp))
          ->size_written = 2 * REG_SIZE;
 
       vec4_instruction *inst = emit(MOV(dst, src_reg(temp2)));
@@ -1128,7 +1128,7 @@ vec4_visitor::nir_emit_alu(nir_alu_instr *instr)
       dst_reg tmp_dst = dst_reg(src_reg(this, glsl_type::dvec4_type));
       src_reg tmp_src = src_reg(this, glsl_type::vec4_type);
       emit(MOV(dst_reg(tmp_src), retype(op[0], BRW_REGISTER_TYPE_F)));
-      emit(VEC4_OPCODE_FLOAT_TO_DOUBLE, tmp_dst, tmp_src);
+      emit(VEC4_OPCODE_TO_DOUBLE, tmp_dst, tmp_src);
       vec4_instruction *inst = emit(MOV(dst, src_reg(tmp_dst)));
       inst->saturate = instr->dest.saturate;
       break;