diff options
| author | Francisco Jerez <[email protected]> | 2016-05-17 15:58:04 -0700 |
|---|---|---|
| committer | Francisco Jerez <[email protected]> | 2016-05-27 23:19:22 -0700 |
| commit | 88d9cc15637559229fe725c0531de8ad7a0a60a7 (patch) | |
| tree | 19ccdb7e854371cd6761721539d66f1ed865bc34 /src/mesa | |
| parent | a6bf5f88c7be5ba1d1d9ebf1412e99886e0cf75c (diff) | |
i965/fs: Implement workaround for IVB CMP dependency race in the SIMD lowering pass.
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs.cpp | 18 |
1 files changed, 17 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs.cpp b/src/mesa/drivers/dri/i965/brw_fs.cpp index b1cd0d959fb..0b7c84a9e40 100644 --- a/src/mesa/drivers/dri/i965/brw_fs.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs.cpp @@ -4739,7 +4739,6 @@ get_lowered_simd_width(const struct brw_device_info *devinfo, case BRW_OPCODE_SHR: case BRW_OPCODE_SHL: case BRW_OPCODE_ASR: - case BRW_OPCODE_CMP: case BRW_OPCODE_CMPN: case BRW_OPCODE_CSEL: case BRW_OPCODE_F32TO16: @@ -4766,6 +4765,23 @@ get_lowered_simd_width(const struct brw_device_info *devinfo, case FS_OPCODE_PACK: return get_fpu_lowered_simd_width(devinfo, inst); + case BRW_OPCODE_CMP: { + /* The Ivybridge/BayTrail WaCMPInstFlagDepClearedEarly workaround says that + * when the destination is a GRF the dependency-clear bit on the flag + * register is cleared early. + * + * Suggested workarounds are to disable coissuing CMP instructions + * or to split CMP(16) instructions into two CMP(8) instructions. + * + * We choose to split into CMP(8) instructions since disabling + * coissuing would affect CMP instructions not otherwise affected by + * the errata. + */ + const unsigned max_width = (devinfo->gen == 7 && !devinfo->is_haswell && + !inst->dst.is_null() ? 8 : ~0); + return MIN2(max_width, get_fpu_lowered_simd_width(devinfo, inst)); + } + case SHADER_OPCODE_RCP: case SHADER_OPCODE_RSQ: case SHADER_OPCODE_SQRT: |