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authorEric Anholt <[email protected]>2009-11-18 03:43:16 -0800
committerEric Anholt <[email protected]>2009-11-19 11:47:21 +0100
commit667760f53c16fae45ab29881c5ea12eef5fcda54 (patch)
tree4a893be2b41a838a0ed6d34e24c1d7e9f9138d33 /src/mesa
parentee64347979b4e22976910cb97869887f7de4241c (diff)
intel: Remove dead intel_context members and move some packing around.
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c6
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h10
2 files changed, 1 insertions, 15 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index 2aeca6b81b0..7b7c0a0b5ae 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -733,12 +733,6 @@ intelInitContext(struct intel_context *intel,
intel->RenderIndex = ~0;
fthrottle_mode = driQueryOptioni(&intel->optionCache, "fthrottle_mode");
- intel->irqsEmitted = 0;
-
- intel->do_irqs = (intel->intelScreen->irq_active &&
- fthrottle_mode == DRI_CONF_FTHROTTLE_IRQS);
-
- intel->do_usleeps = (fthrottle_mode == DRI_CONF_FTHROTTLE_USLEEPS);
if (intel->gen >= 4 && !intel->intelScreen->irq_active) {
_mesa_printf("IRQs not active. Exiting\n");
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index 8cd3efea8a9..f16f502c1d4 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -225,6 +225,7 @@ struct intel_context
GLboolean hw_stipple;
GLboolean depth_buffer_is_float;
GLboolean no_rast;
+ GLboolean no_hw;
GLboolean always_flush_batch;
GLboolean always_flush_cache;
@@ -290,13 +291,6 @@ struct intel_context
GLboolean use_early_z;
drm_clip_rect_t fboRect; /**< cliprect for FBO rendering */
- int perf_boxes;
-
- GLuint do_usleeps;
- int do_irqs;
- GLuint irqsEmitted;
-
- GLboolean scissor;
drm_clip_rect_t draw_rect;
drm_clip_rect_t scissor_rect;
@@ -313,8 +307,6 @@ struct intel_context
GLuint lastStamp;
- GLboolean no_hw;
-
/**
* Configuration cache
*/