diff options
| author | Samuel Iglesias Gonsálvez <[email protected]> | 2016-12-07 10:32:38 +0100 |
|---|---|---|
| committer | Samuel Iglesias Gonsálvez <[email protected]> | 2017-01-05 07:29:13 +0100 |
| commit | 301fdfd8387856ea83c0ac0bff95915c0872c2f4 (patch) | |
| tree | c8431acd62b235621576b75e3ae978d0607dbdf8 /src/mesa | |
| parent | 3fbdac28d55fa765d111ef311761eb145188c142 (diff) | |
vec4: use DIM instruction when loading DF immediates in HSW
Signed-off-by: Samuel Iglesias Gonsálvez <[email protected]>
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_vec4_nir.cpp | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp index 065e3170f10..98e023a66d9 100644 --- a/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp +++ b/src/mesa/drivers/dri/i965/brw_vec4_nir.cpp @@ -1208,6 +1208,15 @@ vec4_visitor::setup_imm_df(double v) if (devinfo->gen >= 8) return brw_imm_df(v); + /* gen7.5 does not support DF immediates straighforward but the DIM + * instruction allows to set the 64-bit immediate value. + */ + if (devinfo->is_haswell) { + dst_reg dst = retype(dst_reg(VGRF, alloc.allocate(2)), BRW_REGISTER_TYPE_DF); + emit(DIM(dst, brw_imm_df(v)))->force_writemask_all = true; + return swizzle(src_reg(retype(dst, BRW_REGISTER_TYPE_DF)), BRW_SWIZZLE_XXXX); + } + /* gen7 does not support DF immediates */ union { double d; |