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authorJason Ekstrand <[email protected]>2018-08-17 09:15:56 -0500
committerJason Ekstrand <[email protected]>2018-08-29 14:04:03 -0500
commitd8033d4083d341f3351c8ca929935617b9b16f3a (patch)
tree8e3267f9bd36084229e790ddde01b49f752ca24a /src/mesa
parent3cbc02e4693030d18a24602cf72e693b92e1a7a3 (diff)
intel/compiler: Remove surface_idx from brw_image_param
Now that the drivers are lowering to surface indices themselves, we no longer need to push the surface index into the shader. Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp3
-rw-r--r--src/mesa/drivers/dri/i965/brw_wm_surface_state.c12
2 files changed, 3 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
index 8a560d9bac1..0b028afdce7 100644
--- a/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
+++ b/src/mesa/drivers/dri/i965/brw_nir_uniforms.cpp
@@ -93,9 +93,6 @@ brw_setup_image_uniform_values(gl_shader_stage stage,
/* Upload the brw_image_param structure. The order is expected to match
* the BRW_IMAGE_PARAM_*_OFFSET defines.
*/
- setup_vec4_image_param(param + BRW_IMAGE_PARAM_SURFACE_IDX_OFFSET,
- image_idx,
- offsetof(brw_image_param, surface_idx), 1);
setup_vec4_image_param(param + BRW_IMAGE_PARAM_OFFSET_OFFSET,
image_idx,
offsetof(brw_image_param, offset), 2);
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
index 35bb49f30f2..42af41aca32 100644
--- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
+++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c
@@ -1474,11 +1474,9 @@ get_image_format(struct brw_context *brw, mesa_format format, GLenum access)
static void
update_default_image_param(struct brw_context *brw,
struct gl_image_unit *u,
- unsigned surface_idx,
struct brw_image_param *param)
{
memset(param, 0, sizeof(*param));
- param->surface_idx = surface_idx;
/* Set the swizzling shifts to all-ones to effectively disable swizzling --
* See emit_address_calculation() in brw_fs_surface_builder.cpp for a more
* detailed explanation of these parameters.
@@ -1490,11 +1488,10 @@ update_default_image_param(struct brw_context *brw,
static void
update_buffer_image_param(struct brw_context *brw,
struct gl_image_unit *u,
- unsigned surface_idx,
struct brw_image_param *param)
{
const unsigned size = buffer_texture_range_size(brw, u->TexObj);
- update_default_image_param(brw, u, surface_idx, param);
+ update_default_image_param(brw, u, param);
param->size[0] = size / _mesa_get_format_bytes(u->_ActualFormat);
param->stride[0] = _mesa_get_format_bytes(u->_ActualFormat);
@@ -1516,7 +1513,6 @@ static void
update_image_surface(struct brw_context *brw,
struct gl_image_unit *u,
GLenum access,
- unsigned surface_idx,
uint32_t *surf_offset,
struct brw_image_param *param)
{
@@ -1538,7 +1534,7 @@ update_image_surface(struct brw_context *brw,
format, buffer_size, texel_size,
written ? RELOC_WRITE : 0);
- update_buffer_image_param(brw, u, surface_idx, param);
+ update_buffer_image_param(brw, u, param);
} else {
struct intel_texture_object *intel_obj = intel_texture_object(obj);
@@ -1575,12 +1571,11 @@ update_image_surface(struct brw_context *brw,
}
isl_surf_fill_image_param(&brw->isl_dev, param, &mt->surf, &view);
- param->surface_idx = surface_idx;
}
} else {
emit_null_surface_state(brw, NULL, surf_offset);
- update_default_image_param(brw, u, surface_idx, param);
+ update_default_image_param(brw, u, param);
}
}
@@ -1599,7 +1594,6 @@ brw_upload_image_surfaces(struct brw_context *brw,
const unsigned surf_idx = prog_data->binding_table.image_start + i;
update_image_surface(brw, u, prog->sh.ImageAccess[i],
- surf_idx,
&stage_state->surf_offset[surf_idx],
&stage_state->image_param[i]);
}