diff options
| author | Caio Marcelo de Oliveira Filho <[email protected]> | 2019-01-31 13:28:24 -0800 |
|---|---|---|
| committer | Caio Marcelo de Oliveira Filho <[email protected]> | 2019-02-04 20:44:41 -0800 |
| commit | 60740eade34993e036f1093f18adf8e5474f3ce5 (patch) | |
| tree | 91784da3c33403ceff2745f391f172cc772d23aa /src/mesa | |
| parent | 51547bbc5a6d889d1d1824c88ac7d0a4b172df55 (diff) | |
i965: skip bit6 swizzle detection in Gen8+
It is always false on Gen8+.
Reviewed-by: Jordan Justen <[email protected]>
Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_screen.c | 14 |
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c index 8838f977bb6..0821d30f3d8 100644 --- a/src/mesa/drivers/dri/i965/intel_screen.c +++ b/src/mesa/drivers/dri/i965/intel_screen.c @@ -1889,6 +1889,20 @@ intel_init_bufmgr(struct intel_screen *screen) static bool intel_detect_swizzling(struct intel_screen *screen) { + /* Broadwell PRM says: + * + * "Before Gen8, there was a historical configuration control field to + * swizzle address bit[6] for in X/Y tiling modes. This was set in three + * different places: TILECTL[1:0], ARB_MODE[5:4], and + * DISP_ARB_CTL[14:13]. + * + * For Gen8 and subsequent generations, the swizzle fields are all + * reserved, and the CPU's memory controller performs all address + * swizzling modifications." + */ + if (screen->devinfo.gen >= 8) + return false; + uint32_t tiling = I915_TILING_X; uint32_t swizzle_mode = 0; struct brw_bo *buffer = |