diff options
| author | Chris Wilson <[email protected]> | 2011-03-03 18:15:03 +0000 |
|---|---|---|
| committer | Chris Wilson <[email protected]> | 2011-03-04 09:58:31 +0000 |
| commit | 18dd7932c7fc13e230384bcab08311a5de5d6de7 (patch) | |
| tree | 91a6e1e76e8034375b0493fcd63d8d3ed6d2d725 /src/mesa | |
| parent | 1546291e5b8d3ac02f5bee38252f9d479bcf95cc (diff) | |
i965: Handle URB_FENCE erratum for Broadwater
There is a silicon bug which causes unpredictable behaviour if the
URB_FENCE command should cross a cache-line boundary. Pad before the
command to avoid such occurrences. As this command only applies to
gen4/5, do the fixup unconditionally as the specs do not actually state
for which chip it was fixed (and the cost is negligible)...
Signed-off-by: Chris Wilson <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_urb.c | 8 |
1 files changed, 8 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_urb.c b/src/mesa/drivers/dri/i965/brw_urb.c index dfc1551aca6..b0419d8a420 100644 --- a/src/mesa/drivers/dri/i965/brw_urb.c +++ b/src/mesa/drivers/dri/i965/brw_urb.c @@ -248,5 +248,13 @@ void brw_upload_urb_fence(struct brw_context *brw) uf.bits1.sf_fence = brw->urb.cs_start; uf.bits1.cs_fence = brw->urb.size; + /* erratum: URB_FENCE must not cross a 64byte cacheline */ + if ((brw->intel.batch.used & 15) > 12) { + int pad = 16 - (brw->intel.batch.used & 15); + do + brw->intel.batch.map[brw->intel.batch.used++] = MI_NOOP; + while (--pad); + } + BRW_BATCH_STRUCT(brw, &uf); } |