diff options
| author | Nicolai Hähnle <[email protected]> | 2016-10-07 16:15:30 +0200 |
|---|---|---|
| committer | Nicolai Hähnle <[email protected]> | 2016-10-12 18:50:10 +0200 |
| commit | 63193b9cdeca4f5d0e91f90c0926a1565f6b0415 (patch) | |
| tree | 2c84ba15ce3c004dab4ade2fa8acb2a1751da81c /src/mesa | |
| parent | f5f3cadca3809952288e3726ed5fde22090dc61d (diff) | |
st/glsl_to_tgsi: disable on-the-fly peephole for 64-bit operations
This optimization is incorrect with 64-bit operations, because the
channel-splitting logic in emit_asm ends up being applied twice to
the source operands.
A lucky coincidence of how the writemask test works resulted in this
optimization basically never being applied anyway. As far as I can tell,
the only case where it would (incorrectly) have been applied is something
like
dvec2 d;
float x = (float)d.y;
which nobody seems to have ever done. But the moral equivalent does occur
in one of the component layout piglit test.
Cc: [email protected]
Reviewed-by: Edward O'Callaghan <[email protected]>
Reviewed-by: Dave Airlie <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/state_tracker/st_glsl_to_tgsi.cpp | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp index 6a63e5c6ec0..dc20fe49c55 100644 --- a/src/mesa/state_tracker/st_glsl_to_tgsi.cpp +++ b/src/mesa/state_tracker/st_glsl_to_tgsi.cpp @@ -255,6 +255,7 @@ public: ir_instruction *ir; GLboolean cond_update; bool saturate; + bool is_64bit_expanded; st_src_reg sampler; /**< sampler register */ int sampler_base; int sampler_array_size; /**< 1-based size of sampler array, 1 if not array */ @@ -670,6 +671,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op, inst->src[1] = src1; inst->src[2] = src2; inst->src[3] = src3; + inst->is_64bit_expanded = false; inst->ir = ir; inst->dead_mask = 0; /* default to float, for paths where this is not initialized @@ -790,6 +792,7 @@ glsl_to_tgsi_visitor::emit_asm(ir_instruction *ir, unsigned op, dinst->prev = NULL; } this->instructions.push_tail(dinst); + dinst->is_64bit_expanded = true; /* modify the destination if we are splitting */ for (j = 0; j < 2; j++) { @@ -2908,6 +2911,7 @@ glsl_to_tgsi_visitor::visit(ir_assignment *ir) } else if (ir->rhs->as_expression() && this->instructions.get_tail() && ir->rhs == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->ir && + !((glsl_to_tgsi_instruction *)this->instructions.get_tail())->is_64bit_expanded && type_size(ir->lhs->type) == 1 && l.writemask == ((glsl_to_tgsi_instruction *)this->instructions.get_tail())->dst[0].writemask) { /* To avoid emitting an extra MOV when assigning an expression to a |