diff options
| author | Roland Scheidegger <[email protected]> | 2007-11-15 01:16:27 +0100 |
|---|---|---|
| committer | Roland Scheidegger <[email protected]> | 2007-11-15 01:16:27 +0100 |
| commit | edfee04fcb1431aa079c69b7c0b67e87de4063c7 (patch) | |
| tree | e2f233e046a27f3a213d0a436b88463da626d901 /src/mesa | |
| parent | 28c9930888ffeb66274c27e9a5f980e115df6ee7 (diff) | |
fix bogus assumption if ddx has set up surface reg for z buffer
this is wrong since even if ddx has not set up a surface reg to cover the z
buffer we should pretend it has on those rv100 chips since they presumably do
not do z buffer tiling if not using hyperz, so we can use linear addressing
just the same. Doesn't seem to fix #13080, but it's wrong anyway and the bug
almost certainly broke newer non-tcl chips.
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/radeon/radeon_screen.c | 3 |
1 files changed, 1 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/radeon/radeon_screen.c b/src/mesa/drivers/dri/radeon/radeon_screen.c index 682cf3a5ee5..c2057eaec68 100644 --- a/src/mesa/drivers/dri/radeon/radeon_screen.c +++ b/src/mesa/drivers/dri/radeon/radeon_screen.c @@ -702,8 +702,7 @@ radeonCreateScreen( __DRIscreenPrivate *sPriv ) screen->depthPitch = dri_priv->depthPitch; /* Check if ddx has set up a surface reg to cover depth buffer */ - screen->depthHasSurface = ((sPriv->ddxMajor > 4) && - (screen->chip_flags & RADEON_CHIPSET_TCL)); + screen->depthHasSurface = (sPriv->ddxMajor > 4); if ( dri_priv->textureSize == 0 ) { screen->texOffset[RADEON_LOCAL_TEX_HEAP] = screen->gart_texture_offset; |