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authorKenneth Graunke <[email protected]>2013-03-26 15:22:22 -0700
committerKenneth Graunke <[email protected]>2013-09-26 16:55:18 -0700
commite5c49bc25b07b76dbcf577186484ab271114c48a (patch)
tree722825038b9e50abb72f364ac7b6b96146a35c2f /src/mesa
parent0f2da773070c06b6d20ad264d3abb19c4dfd9761 (diff)
i965: Add #define for MI_REPORT_PERF_COUNT on Gen6+.
This appears in Volume 1 Part 1 of the Sandybridge PRM on page 48. Signed-off-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_defines.h2
1 files changed, 2 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h
index e2838059050..b14c346abe6 100644
--- a/src/mesa/drivers/dri/i965/brw_defines.h
+++ b/src/mesa/drivers/dri/i965/brw_defines.h
@@ -1825,6 +1825,8 @@ enum brw_wm_barycentric_interp_mode {
# define MI_COUNTER_ADDRESS_GTT (1 << 0)
/* DW2: a user-defined report ID (written to the buffer but can be anything) */
+#define GEN6_MI_REPORT_PERF_COUNT ((0x28 << 23) | (3 - 2))
+
/* Bitfields for the URB_WRITE message, DW2 of message header: */
#define URB_WRITE_PRIM_END 0x1
#define URB_WRITE_PRIM_START 0x2