diff options
| author | Jordan Justen <[email protected]> | 2014-05-01 11:03:09 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2014-11-03 15:33:09 -0800 |
| commit | 5745aaf15cf185d56da680980aaa1ba537f3eb44 (patch) | |
| tree | 3c1894ec73265344f56d73fd54240fc11ad030ca /src/mesa | |
| parent | 35bbe177ecea3fdd06d97d0c13beadb75049ac72 (diff) | |
i965/skl: Implement workaround for VF Invalidate issue
Signed-off-by: Jordan Justen <[email protected]>
Reviewed-by: Kristian Høgsberg <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Reviewed-by: Anuj Phogat <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_batchbuffer.c | 9 |
1 files changed, 9 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c index 71dc268a27b..cd45af6fbe2 100644 --- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c +++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c @@ -648,6 +648,15 @@ intel_batchbuffer_emit_mi_flush(struct brw_context *brw) } else { int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_WRITE_FLUSH; if (brw->gen >= 6) { + if (brw->gen == 9) { + /* Hardware workaround: SKL + * + * Emit Pipe Control with all bits set to zero before emitting + * a Pipe Control with VF Cache Invalidate set. + */ + brw_emit_pipe_control_flush(brw, 0); + } + flags |= PIPE_CONTROL_INSTRUCTION_FLUSH | PIPE_CONTROL_DEPTH_CACHE_FLUSH | PIPE_CONTROL_VF_CACHE_INVALIDATE | |