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authorKenneth Graunke <[email protected]>2013-04-08 19:39:20 -0700
committerKenneth Graunke <[email protected]>2013-04-08 16:15:07 -0700
commitb76539aabea6a910e15d2c626901c7b208868f0c (patch)
tree67227a0de66943f4daaf329de750cb99252a30fb /src/mesa
parent55ecc448b9d05e9f1e5ceb88ab35606e80e3adee (diff)
intel: Remove the texture_tiling driconf option.
This option can force textures to be untiled. However, on Gen6+, depth buffers must be Y-tiled. MSAA buffers also must be Y-tiled. So setting this option on even a trivial application like glxgears causes assertion failures in a debug build, and likely GPU hangs in a release build. It's just giving users a license to shoot themselves in the foot. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.c2
-rw-r--r--src/mesa/drivers/dri/intel/intel_context.h1
-rw-r--r--src/mesa/drivers/dri/intel/intel_mipmap_tree.c3
-rw-r--r--src/mesa/drivers/dri/intel/intel_screen.c6
4 files changed, 1 insertions, 11 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_context.c b/src/mesa/drivers/dri/intel/intel_context.c
index bf4045eb3b6..990fbeab5d1 100644
--- a/src/mesa/drivers/dri/intel/intel_context.c
+++ b/src/mesa/drivers/dri/intel/intel_context.c
@@ -811,8 +811,6 @@ intelInitContext(struct intel_context *intel,
intel_fbo_init(intel);
- intel->use_texture_tiling = driQueryOptionb(&intel->optionCache,
- "texture_tiling");
intel->use_early_z = driQueryOptionb(&intel->optionCache, "early_z");
if (!driQueryOptionb(&intel->optionCache, "hiz")) {
diff --git a/src/mesa/drivers/dri/intel/intel_context.h b/src/mesa/drivers/dri/intel/intel_context.h
index b2ded4924b2..22d29be278b 100644
--- a/src/mesa/drivers/dri/intel/intel_context.h
+++ b/src/mesa/drivers/dri/intel/intel_context.h
@@ -343,7 +343,6 @@ struct intel_context
*/
bool is_front_buffer_reading;
- bool use_texture_tiling;
bool use_early_z;
int driFd;
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index 38c0149b262..19c9088791a 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -316,9 +316,6 @@ intel_miptree_choose_tiling(struct intel_context *intel,
return I915_TILING_NONE;
}
- if (!intel->use_texture_tiling)
- return I915_TILING_NONE;
-
if (force_y_tiling)
return I915_TILING_Y;
diff --git a/src/mesa/drivers/dri/intel/intel_screen.c b/src/mesa/drivers/dri/intel/intel_screen.c
index 58496e232c9..16750f2717e 100644
--- a/src/mesa/drivers/dri/intel/intel_screen.c
+++ b/src/mesa/drivers/dri/intel/intel_screen.c
@@ -55,10 +55,6 @@ PUBLIC const char __driConfigOptions[] =
DRI_CONF_DESC_END
DRI_CONF_OPT_END
- DRI_CONF_OPT_BEGIN(texture_tiling, bool, true)
- DRI_CONF_DESC(en, "Enable texture tiling")
- DRI_CONF_OPT_END
-
DRI_CONF_OPT_BEGIN(hiz, bool, true)
DRI_CONF_DESC(en, "Enable Hierarchical Z on gen6+")
DRI_CONF_OPT_END
@@ -95,7 +91,7 @@ PUBLIC const char __driConfigOptions[] =
DRI_CONF_SECTION_END
DRI_CONF_END;
-const GLuint __driNConfigOptions = 17;
+const GLuint __driNConfigOptions = 16;
#include "intel_batchbuffer.h"
#include "intel_buffers.h"