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authorJason Ekstrand <[email protected]>2018-05-09 15:06:13 -0700
committerJason Ekstrand <[email protected]>2018-05-09 18:03:28 -0700
commita8a740f272a808a2694524b43fc33d2f0c0e3709 (patch)
tree88cac61454d25170af4a236e572abf13c9ad84d0 /src/mesa
parent56766b8515bf73a0f4fc84fad81ba808a520391a (diff)
i965,anv: Set the CS stall bit on the ISP disable PIPE_CONTROL
From the bspec docs for "Indirect State Pointers Disable": "At the completion of the post-sync operation associated with this pipe control packet, the indirect state pointers in the hardware are considered invalid" So the ISP disable is a post-sync type of operation which means that it should be combined with a CS stall. Without this, the simulator throws an error. Fixes: 766d801ca "anv: emit pixel scoreboard stall before ISP disable" Fixes: f536097f6 "i965: require pixel scoreboard stall prior to ISP disable" Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_pipe_control.c3
1 files changed, 2 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c
index 879bfb660ed..e31d625ddba 100644
--- a/src/mesa/drivers/dri/i965/brw_pipe_control.c
+++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c
@@ -362,7 +362,8 @@ gen10_emit_isp_disable(struct brw_context *brw)
PIPE_CONTROL_CS_STALL,
NULL, 0, 0);
brw_emit_pipe_control(brw,
- PIPE_CONTROL_ISP_DIS,
+ PIPE_CONTROL_ISP_DIS |
+ PIPE_CONTROL_CS_STALL,
NULL, 0, 0);
brw->vs.base.push_constants_dirty = true;