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authorEric Anholt <[email protected]>2012-12-12 12:47:50 -0800
committerEric Anholt <[email protected]>2012-12-14 15:45:26 -0800
commit7baf9198b201666fc0f20fe407d7b46ee0ca7ef5 (patch)
tree31805ce51bf0909138615ee7bd36b0ea30479565 /src/mesa
parent2702202290b55a9c8b61f02f7ae0af8f4a53f0e2 (diff)
i965: Also consider HALTs a potential block end.
The final halt of the fragment shader turns off the remaining channels, then jumps such that everything is turned back on. So, we can have our last ENDIF of the shader point at that directly. Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/brw_eu_emit.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c
index c294bae74d9..8a93ced760f 100644
--- a/src/mesa/drivers/dri/i965/brw_eu_emit.c
+++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c
@@ -2317,6 +2317,7 @@ brw_find_next_block_end(struct brw_compile *p, int start)
case BRW_OPCODE_ENDIF:
case BRW_OPCODE_ELSE:
case BRW_OPCODE_WHILE:
+ case BRW_OPCODE_HALT:
return ip;
}
}