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authorKenneth Graunke <[email protected]>2012-11-29 01:50:22 -0800
committerKenneth Graunke <[email protected]>2014-01-31 17:50:06 -0800
commit4552a22f0425149f9bb5722af46c1c8766ddc8db (patch)
tree438cc05a29de95ca9bcfbd95155d45e296d32162 /src/mesa
parent2184b519cd2cbb7163d4757afb8d8dc193864c4d (diff)
i965: Bump generation assertions on workaround flushes.
I haven't investigated whether these are necessary on Broadwell or not, but for paranoia's sake, we may as well continue doing them for now. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/intel_batchbuffer.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_batchbuffer.c b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
index caec3125565..fbbd5274f13 100644
--- a/src/mesa/drivers/dri/i965/intel_batchbuffer.c
+++ b/src/mesa/drivers/dri/i965/intel_batchbuffer.c
@@ -529,7 +529,7 @@ brw_emit_pipe_control_write(struct brw_context *brw, uint32_t flags,
void
intel_emit_depth_stall_flushes(struct brw_context *brw)
{
- assert(brw->gen >= 6 && brw->gen <= 7);
+ assert(brw->gen >= 6 && brw->gen <= 8);
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_STALL);
brw_emit_pipe_control_flush(brw, PIPE_CONTROL_DEPTH_CACHE_FLUSH);
@@ -547,7 +547,7 @@ intel_emit_depth_stall_flushes(struct brw_context *brw)
void
gen7_emit_vs_workaround_flush(struct brw_context *brw)
{
- assert(brw->gen == 7);
+ assert(brw->gen >= 7 && brw->gen <= 8);
brw_emit_pipe_control_write(brw,
PIPE_CONTROL_WRITE_IMMEDIATE
| PIPE_CONTROL_DEPTH_STALL,