diff options
| author | Anuj Phogat <[email protected]> | 2017-11-03 14:48:29 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-02-15 16:14:56 -0800 |
| commit | 3f8289164f6d910bdf62e4b55c6ccb22dec90417 (patch) | |
| tree | 59f6a08be77d4eb6e64f250f047144f37696cdf6 /src/mesa | |
| parent | ba3cbee6c56a31ca1513f9c2b205f2c0174d9e60 (diff) | |
i965/icl: Enable float blend optimization and Wa3DStateMode
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 2c8c0f4b278..86c12e4d357 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -62,7 +62,7 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_upload_invariant_state(brw); - if (devinfo->gen == 10) { + if (devinfo->gen == 10 || devinfo->gen == 11) { brw_load_register_imm32(brw, GEN10_CACHE_MODE_SS, REG_MASK(GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE) | GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE); |