diff options
| author | Abdiel Janulgue <[email protected]> | 2012-11-28 12:34:21 +0200 |
|---|---|---|
| committer | Chad Versace <[email protected]> | 2013-02-01 11:58:12 -0800 |
| commit | 45a28a927ab7f29ff325b9326d386a39ba538c18 (patch) | |
| tree | d19f4184a2312eccc1b548c2d1c99079164cbe6d /src/mesa | |
| parent | 163b35e416349c0f079aa6a92eb0bade2cabf5bc (diff) | |
i965: Account for offsets when updating SURFACE_STATE.
If the offsets are present, this lets us specify a particular level and slice
in a shared region using the base level of an exported mip-map tree.
Reviewed-by: Eric Anholt <[email protected]>
Reviewed-by: Chad Versace <[email protected]>
Signed-off-by: Abdiel Janulgue <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 12 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 11 |
2 files changed, 21 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index 7f7b7ebe2b0..e732b6d9b8e 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -837,6 +837,7 @@ brw_update_texture_surface(struct gl_context *ctx, struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); uint32_t *surf; int width, height, depth; + uint32_t tile_x, tile_y; if (tObj->Target == GL_TEXTURE_BUFFER) { brw_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); @@ -870,7 +871,16 @@ brw_update_texture_surface(struct gl_context *ctx, surf[4] = 0; - surf[5] = (mt->align_h == 4) ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0; + intel_miptree_get_tile_offsets(intelObj->mt, 0, 0, &tile_x, &tile_y); + assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); + /* Note that the low bits of these fields are missing, so + * there's the possibility of getting in trouble. + */ + assert(tile_x % 4 == 0); + assert(tile_y % 2 == 0); + surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | + (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | + (mt->align_h == 4 ? BRW_SURFACE_VERTICAL_ALIGN_ENABLE : 0)); /* Emit relocation to surface contents */ drm_intel_bo_emit_reloc(brw->intel.batch.bo, diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 236d50c8bc3..9c8bc17d5cb 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -292,6 +292,7 @@ gen7_update_texture_surface(struct gl_context *ctx, struct gl_texture_image *firstImage = tObj->Image[0][tObj->BaseLevel]; struct gl_sampler_object *sampler = _mesa_get_samplerobj(ctx, unit); int width, height, depth; + uint32_t tile_x, tile_y; if (tObj->Target == GL_TEXTURE_BUFFER) { gen7_update_buffer_texture_surface(ctx, unit, binding_table, surf_index); @@ -333,7 +334,15 @@ gen7_update_texture_surface(struct gl_context *ctx, surf[3] = SET_FIELD(depth - 1, BRW_SURFACE_DEPTH) | ((intelObj->mt->region->pitch) - 1); - surf[5] = intelObj->_MaxLevel - tObj->BaseLevel; /* mip count */ + intel_miptree_get_tile_offsets(intelObj->mt, 0, 0, &tile_x, &tile_y); + assert(brw->has_surface_tile_offset || (tile_x == 0 && tile_y == 0)); + /* Note that the low bits of these fields are missing, so + * there's the possibility of getting in trouble. + */ + surf[5] = ((tile_x / 4) << BRW_SURFACE_X_OFFSET_SHIFT | + (tile_y / 2) << BRW_SURFACE_Y_OFFSET_SHIFT | + /* mip count */ + (intelObj->_MaxLevel - tObj->BaseLevel)); if (intel->is_haswell) { /* Handling GL_ALPHA as a surface format override breaks 1.30+ style |