diff options
| author | Kenneth Graunke <[email protected]> | 2015-12-09 21:42:56 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2015-12-14 14:48:29 -0800 |
| commit | 9f0944d15b9d2cd85f501f80eea7e6b6fc7f3487 (patch) | |
| tree | ae8afff3156daf541217cdf83887fb7c07380ddc /src/mesa | |
| parent | 4fac9500100273424450b5687c4e04dfd066d08e (diff) | |
i965: Make TES inputs match TCS outputs.
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Jordan Justen <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_nir.c | 11 |
1 files changed, 11 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_nir.c b/src/mesa/drivers/dri/i965/brw_nir.c index 38706a0699c..2b90966b1ec 100644 --- a/src/mesa/drivers/dri/i965/brw_nir.c +++ b/src/mesa/drivers/dri/i965/brw_nir.c @@ -636,6 +636,17 @@ brw_create_nir(struct brw_context *brw, /* First, lower the GLSL IR or Mesa IR to NIR */ if (shader_prog) { nir = glsl_to_nir(shader_prog, stage, options); + + if (nir->stage == MESA_SHADER_TESS_EVAL && + shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]) { + const struct gl_program *tcs = + shader_prog->_LinkedShaders[MESA_SHADER_TESS_CTRL]->Program; + /* Work around the TCS having bonus outputs used as shared memory + * segments, which makes OutputsWritten not match InputsRead + */ + nir->info.inputs_read = tcs->OutputsWritten; + nir->info.patch_inputs_read = tcs->PatchOutputsWritten; + } } else { nir = prog_to_nir(prog, options); OPT_V(nir_convert_to_ssa); /* turn registers into SSA */ |