diff options
| author | Anuj Phogat <[email protected]> | 2017-11-09 11:30:10 -0800 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2017-11-14 13:23:18 -0800 |
| commit | 1dc45d75bb3ff3085f7356b8ec658111529ff76d (patch) | |
| tree | 001b84cb3c2475a541e5da4770f351c320f74939 /src/mesa | |
| parent | 6165fda59b889de035b38d9a1a08ffe0da19e6a6 (diff) | |
i965/gen8+: Fix the number of dwords programmed in MI_FLUSH_DW
Number of dwords in MI_FLUSH_DW changed from 4 to 5 in gen8+.
Signed-off-by: Anuj Phogat <[email protected]>
Cc: <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_pipe_control.c | 7 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_blit.c | 17 |
2 files changed, 19 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_pipe_control.c b/src/mesa/drivers/dri/i965/brw_pipe_control.c index 35f326a5c55..39e8bff7309 100644 --- a/src/mesa/drivers/dri/i965/brw_pipe_control.c +++ b/src/mesa/drivers/dri/i965/brw_pipe_control.c @@ -461,11 +461,14 @@ brw_emit_mi_flush(struct brw_context *brw) const struct gen_device_info *devinfo = &brw->screen->devinfo; if (brw->batch.ring == BLT_RING && devinfo->gen >= 6) { - BEGIN_BATCH_BLT(4); - OUT_BATCH(MI_FLUSH_DW | (4 - 2)); + const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4; + BEGIN_BATCH_BLT(n_dwords); + OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); + if (n_dwords == 5) + OUT_BATCH(0); ADVANCE_BATCH(); } else { int flags = PIPE_CONTROL_NO_WRITE | PIPE_CONTROL_RENDER_TARGET_FLUSH; diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c index 3d7bc92d137..5f25bfaf616 100644 --- a/src/mesa/drivers/dri/i965/intel_blit.c +++ b/src/mesa/drivers/dri/i965/intel_blit.c @@ -101,13 +101,17 @@ set_blitter_tiling(struct brw_context *brw, bool dst_y_tiled, bool src_y_tiled, uint32_t *__map) { - assert(brw->screen->devinfo.gen >= 6); + const struct gen_device_info *devinfo = &brw->screen->devinfo; + const unsigned n_dwords = devinfo->gen >= 8 ? 5 : 4; + assert(devinfo->gen >= 6); /* Idle the blitter before we update how tiling is interpreted. */ - OUT_BATCH(MI_FLUSH_DW | (4 - 2)); + OUT_BATCH(MI_FLUSH_DW | (n_dwords - 2)); OUT_BATCH(0); OUT_BATCH(0); OUT_BATCH(0); + if (n_dwords == 5) + OUT_BATCH(0); OUT_BATCH(MI_LOAD_REGISTER_IMM | (3 - 2)); OUT_BATCH(BCS_SWCTRL); @@ -119,7 +123,14 @@ set_blitter_tiling(struct brw_context *brw, #define SET_BLITTER_TILING(...) __map = set_blitter_tiling(__VA_ARGS__, __map) #define BEGIN_BATCH_BLT_TILED(n, dst_y_tiled, src_y_tiled) \ - BEGIN_BATCH_BLT(n + ((dst_y_tiled || src_y_tiled) ? 14 : 0)); \ + unsigned set_tiling_batch_size = 0; \ + if (dst_y_tiled || src_y_tiled) { \ + if (devinfo->gen >= 8) \ + set_tiling_batch_size = 16; \ + else \ + set_tiling_batch_size = 14; \ + } \ + BEGIN_BATCH_BLT(n + set_tiling_batch_size); \ if (dst_y_tiled || src_y_tiled) \ SET_BLITTER_TILING(brw, dst_y_tiled, src_y_tiled) |