diff options
| author | Anuj Phogat <[email protected]> | 2018-10-02 09:10:04 -0700 |
|---|---|---|
| committer | Anuj Phogat <[email protected]> | 2018-11-01 12:00:23 -0700 |
| commit | b3d6937fb0d31baa77a3caf519458a86de8d202d (patch) | |
| tree | 7db7fbf6e88fc49fe8095540a8139345cd8a3c69 /src/mesa | |
| parent | ac95a0e024c467100138446f031a63916a906876 (diff) | |
i965/icl: Set Error Detection Behavior Control Bit in L3CNTLREG
The default setting of this bit is not the desirable behavior.
WA_1406697149
Signed-off-by: Anuj Phogat <[email protected]>
Reviewed-by: Lionel Landwerlin <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_defines.h | 1 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_state_upload.c | 7 |
2 files changed, 8 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_defines.h b/src/mesa/drivers/dri/i965/brw_defines.h index 97a787a2ab3..897c91aa31e 100644 --- a/src/mesa/drivers/dri/i965/brw_defines.h +++ b/src/mesa/drivers/dri/i965/brw_defines.h @@ -1646,6 +1646,7 @@ enum brw_pixel_shader_coverage_mask_mode { # define GEN8_L3CNTLREG_DC_ALLOC_MASK INTEL_MASK(24, 18) # define GEN8_L3CNTLREG_ALL_ALLOC_SHIFT 25 # define GEN8_L3CNTLREG_ALL_ALLOC_MASK INTEL_MASK(31, 25) +# define GEN8_L3CNTLREG_EDBC_NO_HANG (1 << 9) #define GEN10_CACHE_MODE_SS 0x0e420 #define GEN10_FLOAT_BLEND_OPTIMIZATION_ENABLE (1 << 4) diff --git a/src/mesa/drivers/dri/i965/brw_state_upload.c b/src/mesa/drivers/dri/i965/brw_state_upload.c index 7f20579fb87..60b72bf4ab3 100644 --- a/src/mesa/drivers/dri/i965/brw_state_upload.c +++ b/src/mesa/drivers/dri/i965/brw_state_upload.c @@ -79,6 +79,13 @@ brw_upload_initial_gpu_state(struct brw_context *brw) brw_load_register_imm32(brw, HALF_SLICE_CHICKEN7, TEXEL_OFFSET_FIX_MASK | TEXEL_OFFSET_FIX_ENABLE); + + /* WA_1406697149: Bit 9 "Error Detection Behavior Control" must be set + * in L3CNTLREG register. The default setting of the bit is not the + * desirable behavior. + */ + brw_load_register_imm32(brw, GEN8_L3CNTLREG, + GEN8_L3CNTLREG_EDBC_NO_HANG); } if (devinfo->gen == 10 || devinfo->gen == 11) { |