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authorPaul Berry <stereotype441@gmail.com>2011-10-07 17:37:32 -0700
committerPaul Berry <stereotype441@gmail.com>2011-10-31 11:24:03 -0700
commitf40c6b2a992f3ca796826a47743c0c80232d7ab2 (patch)
tree3d5628654aa3e69154d0fe236ffb8756a388f881 /src/mesa
parentede60bc4670a8d9c14921c77abee1ac57fc0e6bf (diff)
i965/gen6+: Switch GLSL from ALT to IEEE floating point mode
i965 graphics hardware has two floating point modes: ALT and IEEE. In ALT mode, floating-point operations never generate infinities or NaNs, and MOV instructions translate infinities and NaNs to finite values. In IEEE mode, infinities and NaNs behave as specified in the IEEE 754 spec. Previously, we used ALT mode for all vertex and fragment programs, whether they were GLSL programs or ARB programs. The GLSL spec is sufficiently vague about how infs and nans are to be handled that it was unclear whether this mode was compliant with the GLSL 1.30 spec or not, and it made it very difficult to test the isinf() and isnan() functions. This patch changes i965 GLSL programs to use IEEE floating-point mode, which is clearly compliant with GLSL 1.30's inf/nan requirements. In addition to making the Piglit isinf and isnan tests pass, this paves the way for future support of the ARB_shader_precision extension. Unfortunately we still have to use ALT floating-point mode when executing ARB programs, because those programs require 0^0 == 1, and i965 hardware generates 0^0 == NaN in IEEE mode. Fixes piglit tests "isinf-and-isnan fs_fbo", "isinf-and-isnan vs_fbo", and {fs,vs}-{isinf,isnan}-{vec2,vec3,vec4}.
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/gen6_vs_state.c9
-rw-r--r--src/mesa/drivers/dri/i965/gen6_wm_state.c7
-rw-r--r--src/mesa/drivers/dri/i965/gen7_vs_state.c9
-rw-r--r--src/mesa/drivers/dri/i965/gen7_wm_state.c7
4 files changed, 26 insertions, 6 deletions
diff --git a/src/mesa/drivers/dri/i965/gen6_vs_state.c b/src/mesa/drivers/dri/i965/gen6_vs_state.c
index e06c7b452a0..e22fd393ef5 100644
--- a/src/mesa/drivers/dri/i965/gen6_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_vs_state.c
@@ -131,6 +131,7 @@ static void
upload_vs_state(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
+ uint32_t floating_point_mode = 0;
if (brw->vs.push_const_size == 0) {
/* Disable the push constant buffers. */
@@ -157,11 +158,17 @@ upload_vs_state(struct brw_context *brw)
ADVANCE_BATCH();
}
+ /* Use ALT floating point mode for ARB vertex programs, because they
+ * require 0^0 == 1.
+ */
+ if (intel->ctx.Shader.CurrentVertexProgram == NULL)
+ floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
+
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
OUT_BATCH(brw->vs.prog_offset);
OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
- GEN6_VS_FLOATING_POINT_MODE_ALT |
+ floating_point_mode |
(brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
if (brw->vs.prog_data->total_scratch) {
diff --git a/src/mesa/drivers/dri/i965/gen6_wm_state.c b/src/mesa/drivers/dri/i965/gen6_wm_state.c
index 25e0fa2909e..714d59492ca 100644
--- a/src/mesa/drivers/dri/i965/gen6_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen6_wm_state.c
@@ -134,8 +134,11 @@ upload_wm_state(struct brw_context *brw)
dw5 |= GEN6_WM_LINE_AA_WIDTH_1_0;
dw5 |= GEN6_WM_LINE_END_CAP_AA_WIDTH_0_5;
- /* OpenGL non-ieee floating point mode */
- dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
+ /* Use ALT floating point mode for ARB fragment programs, because they
+ * require 0^0 == 1.
+ */
+ if (ctx->Shader.CurrentFragmentProgram == NULL)
+ dw2 |= GEN6_WM_FLOATING_POINT_MODE_ALT;
/* BRW_NEW_NR_WM_SURFACES */
dw2 |= brw->wm.nr_surfaces << GEN6_WM_BINDING_TABLE_ENTRY_COUNT_SHIFT;
diff --git a/src/mesa/drivers/dri/i965/gen7_vs_state.c b/src/mesa/drivers/dri/i965/gen7_vs_state.c
index 4ef9c688315..dbf93465e49 100644
--- a/src/mesa/drivers/dri/i965/gen7_vs_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_vs_state.c
@@ -33,6 +33,7 @@ static void
upload_vs_state(struct brw_context *brw)
{
struct intel_context *intel = &brw->intel;
+ uint32_t floating_point_mode = 0;
BEGIN_BATCH(2);
OUT_BATCH(_3DSTATE_BINDING_TABLE_POINTERS_VS << 16 | (2 - 2));
@@ -65,11 +66,17 @@ upload_vs_state(struct brw_context *brw)
ADVANCE_BATCH();
}
+ /* Use ALT floating point mode for ARB vertex programs, because they
+ * require 0^0 == 1.
+ */
+ if (intel->ctx.Shader.CurrentVertexProgram == NULL)
+ floating_point_mode = GEN6_VS_FLOATING_POINT_MODE_ALT;
+
BEGIN_BATCH(6);
OUT_BATCH(_3DSTATE_VS << 16 | (6 - 2));
OUT_BATCH(brw->vs.prog_offset);
OUT_BATCH((0 << GEN6_VS_SAMPLER_COUNT_SHIFT) |
- GEN6_VS_FLOATING_POINT_MODE_ALT |
+ floating_point_mode |
(brw->vs.nr_surfaces << GEN6_VS_BINDING_TABLE_ENTRY_COUNT_SHIFT));
if (brw->vs.prog_data->total_scratch) {
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_state.c b/src/mesa/drivers/dri/i965/gen7_wm_state.c
index ba83340bde9..2dce359ea94 100644
--- a/src/mesa/drivers/dri/i965/gen7_wm_state.c
+++ b/src/mesa/drivers/dri/i965/gen7_wm_state.c
@@ -149,8 +149,11 @@ upload_ps_state(struct brw_context *brw)
/* BRW_NEW_NR_WM_SURFACES */
dw2 |= brw->wm.nr_surfaces << GEN7_PS_BINDING_TABLE_ENTRY_COUNT_SHIFT;
- /* OpenGL non-ieee floating point mode */
- dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
+ /* Use ALT floating point mode for ARB fragment programs, because they
+ * require 0^0 == 1.
+ */
+ if (intel->ctx.Shader.CurrentFragmentProgram == NULL)
+ dw2 |= GEN7_PS_FLOATING_POINT_MODE_ALT;
/* CACHE_NEW_SAMPLER */
dw4 |= (brw->max_wm_threads - 1) << GEN7_PS_MAX_THREADS_SHIFT;