glsl: Allow vector logic ops to be generated.

They're not accessible from the source language, but optimizations are
allowed to generate them.

Reviewed-by: Ian Romanick <[email protected]>

1 files changed, 3 insertions, 6 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
index 933fdde24f9..4049b09797c 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_channel_expressions.cpp
@@ -271,6 +271,9 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
    case ir_binop_bit_and:
    case ir_binop_bit_xor:
    case ir_binop_bit_or:
+   case ir_binop_logic_and:
+   case ir_binop_logic_xor:
+   case ir_binop_logic_or:
    case ir_binop_less:
    case ir_binop_greater:
    case ir_binop_lequal:
@@ -329,12 +332,6 @@ ir_channel_expressions_visitor::visit_leave(ir_assignment *ir)
       break;
    }
 
-   case ir_binop_logic_and:
-   case ir_binop_logic_xor:
-   case ir_binop_logic_or:
-      ir->fprint(stderr);
-      fprintf(stderr, "\n");
-      unreachable("not reached: expression operates on scalars only");
    case ir_binop_all_equal:
    case ir_binop_any_nequal: {
       ir_expression *last = NULL;