diff options
| author | Chad Versace <[email protected]> | 2017-05-26 14:53:22 -0700 |
|---|---|---|
| committer | Chad Versace <[email protected]> | 2017-05-30 12:01:38 -0700 |
| commit | 9601b41a33bf6594366eedf6cc4d1c88804a41b7 (patch) | |
| tree | 41dd9cbf26613fc5f000c28362dc9502e0363c4c /src/mesa | |
| parent | 6e325f12030698392ea8ca0d1be4eb95655209a7 (diff) | |
i965: Fix type of brw_context::render_target_format[]
It's an array of isl_format, not uint32_t. This patch updates every
reference to render_target_format[] git-grep.
Trivial cleanup. No change in behavior.
Reviewed-by: Tapani Pälli <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_blorp.c | 4 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 2 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_wm_surface_state.c | 4 |
3 files changed, 5 insertions, 5 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_blorp.c b/src/mesa/drivers/dri/i965/brw_blorp.c index 7ffe8b885a0..9030fe7e760 100644 --- a/src/mesa/drivers/dri/i965/brw_blorp.c +++ b/src/mesa/drivers/dri/i965/brw_blorp.c @@ -920,7 +920,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, struct blorp_batch batch; blorp_batch_init(&brw->blorp, &batch, brw, 0); blorp_fast_clear(&batch, &surf, - (enum isl_format)brw->render_target_format[format], + brw->render_target_format[format], level, logical_layer, num_layers, x0, y0, x1, y1); blorp_batch_finish(&batch); @@ -946,7 +946,7 @@ do_single_blorp_clear(struct brw_context *brw, struct gl_framebuffer *fb, struct blorp_batch batch; blorp_batch_init(&brw->blorp, &batch, brw, 0); blorp_clear(&batch, &surf, - (enum isl_format)brw->render_target_format[format], + brw->render_target_format[format], ISL_SWIZZLE_IDENTITY, level, irb_logical_mt_layer(irb), num_layers, x0, y0, x1, y1, diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index f45fc2479c0..c15abe1d48f 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -1161,7 +1161,7 @@ struct brw_context const struct brw_tracked_state render_atoms[76]; const struct brw_tracked_state compute_atoms[11]; - uint32_t render_target_format[MESA_FORMAT_COUNT]; + enum isl_format render_target_format[MESA_FORMAT_COUNT]; bool format_supported_as_render_target[MESA_FORMAT_COUNT]; /* PrimitiveRestart */ diff --git a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c index a0fed6096d2..e019adcf2df 100644 --- a/src/mesa/drivers/dri/i965/brw_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/brw_wm_surface_state.c @@ -986,7 +986,7 @@ gen4_update_renderbuffer_surface(struct brw_context *brw, struct intel_mipmap_tree *mt = irb->mt; uint32_t *surf; uint32_t tile_x, tile_y; - uint32_t format = 0; + enum isl_format format; uint32_t offset; /* _NEW_BUFFERS */ mesa_format rb_format = _mesa_get_render_format(ctx, intel_rb_format(irb)); @@ -1172,7 +1172,7 @@ update_renderbuffer_read_surfaces(struct brw_context *brw) uint32_t *surf_offset = &brw->wm.base.surf_offset[surf_index]; if (irb) { - const unsigned format = brw->render_target_format[ + const enum isl_format format = brw->render_target_format[ _mesa_get_render_format(ctx, intel_rb_format(irb))]; assert(isl_format_supports_sampling(&brw->screen->devinfo, format)); |