i965/eu: Remove brw_codegen::compressed and ::compressed_stack.

Reviewed-by: Jason Ekstrand <[email protected]>

3 files changed, 5 insertions, 11 deletions

diff --git a/src/mesa/drivers/dri/i965/brw_eu.c b/src/mesa/drivers/dri/i965/brw_eu.c
index 7bb4c7f2aae..cc252de1cd6 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.c
+++ b/src/mesa/drivers/dri/i965/brw_eu.c
@@ -187,8 +187,6 @@ void
 brw_set_default_compression_control(struct brw_codegen *p,
 			    enum brw_compression compression_control)
 {
-   p->compressed = (compression_control == BRW_COMPRESSION_COMPRESSED);
-
    if (p->devinfo->gen >= 6) {
       /* Since we don't use the SIMD32 support in gen6, we translate
        * the pre-gen6 compression control here.
@@ -307,7 +305,6 @@ void brw_push_insn_state( struct brw_codegen *p )
 {
    assert(p->current != &p->stack[BRW_EU_MAX_INSN_STACK-1]);
    memcpy(p->current + 1, p->current, sizeof(brw_inst));
-   p->compressed_stack[p->current - p->stack] = p->compressed;
    p->current++;
 }
 
@@ -315,7 +312,6 @@ void brw_pop_insn_state( struct brw_codegen *p )
 {
    assert(p->current != p->stack);
    p->current--;
-   p->compressed = p->compressed_stack[p->current - p->stack];
 }
 
 
@@ -337,7 +333,6 @@ brw_init_codegen(const struct brw_device_info *devinfo,
    p->store = rzalloc_array(mem_ctx, brw_inst, p->store_size);
    p->nr_insn = 0;
    p->current = p->stack;
-   p->compressed = false;
    memset(p->current, 0, sizeof(p->current[0]));
 
    p->mem_ctx = mem_ctx;
diff --git a/src/mesa/drivers/dri/i965/brw_eu.h b/src/mesa/drivers/dri/i965/brw_eu.h
index 03400aeb54a..91e340190d2 100644
--- a/src/mesa/drivers/dri/i965/brw_eu.h
+++ b/src/mesa/drivers/dri/i965/brw_eu.h
@@ -66,7 +66,6 @@ struct brw_codegen {
    brw_inst *current;
 
    bool single_program_flow;
-   bool compressed;
    const struct brw_device_info *devinfo;
 
    /* Control flow stacks:
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
index 39a76ebf62a..9d7ad5ba24f 100644
--- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
+++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp
@@ -1594,13 +1594,14 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
        *       type and regioning so the instruction is considered compressed
        *       or not accordingly.
        */
-      p->compressed = inst->dst.component_size(inst->exec_size) > REG_SIZE;
-      brw_set_default_compression(p, p->compressed);
+      const bool compressed =
+           inst->dst.component_size(inst->exec_size) > REG_SIZE;
+      brw_set_default_compression(p, compressed);
       brw_set_default_group(p, inst->force_sechalf ? 8 : 0);
 
       for (unsigned int i = 0; i < inst->sources; i++) {
          src[i] = brw_reg_from_fs_reg(inst, &inst->src[i], devinfo->gen,
-                                      p->compressed);
+                                      compressed);
 
 	 /* The accumulator result appears to get used for the
 	  * conditional modifier generation.  When negating a UD
@@ -1612,8 +1613,7 @@ fs_generator::generate_code(const cfg_t *cfg, int dispatch_width)
 		inst->src[i].type != BRW_REGISTER_TYPE_UD ||
 		!inst->src[i].negate);
       }
-      dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen,
-                                p->compressed);
+      dst = brw_reg_from_fs_reg(inst, &inst->dst, devinfo->gen, compressed);
 
       brw_set_default_access_mode(p, BRW_ALIGN_1);
       brw_set_default_predicate_control(p, inst->predicate);