summaryrefslogtreecommitdiffstats
path: root/src/mesa
diff options
context:
space:
mode:
authorRoland Scheidegger <rscheidegger@gmx.ch>2004-06-28 22:32:38 +0000
committerRoland Scheidegger <rscheidegger@gmx.ch>2004-06-28 22:32:38 +0000
commit26755698c8b8981be8778527c4381d69f790e291 (patch)
tree850a9fd29091e3cc7f8a4166ba61c1f8a80c9cc3 /src/mesa
parentdbe1ecaa1d82be41c1d2f2ae2e78e8bd69a62b19 (diff)
add missing R200_RB3D_BLENDCOLOR to r200/radeon_sanity.c
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/r200/r200_sanity.c5
-rw-r--r--src/mesa/drivers/dri/radeon/radeon_sanity.c1
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r200/r200_sanity.c b/src/mesa/drivers/dri/r200/r200_sanity.c
index a21495df4ea..2de262ede33 100644
--- a/src/mesa/drivers/dri/r200/r200_sanity.c
+++ b/src/mesa/drivers/dri/r200/r200_sanity.c
@@ -139,6 +139,10 @@ static struct {
{ R200_PP_CUBIC_OFFSET_F1_4, 5, "R200_PP_CUBIC_OFFSET_F1_4" },
{ R200_PP_CUBIC_FACES_5, 1, "R200_PP_CUBIC_FACES_5" },
{ R200_PP_CUBIC_OFFSET_F1_5, 5, "R200_PP_CUBIC_OFFSET_F1_5" },
+ { RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
+ { RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
+ { RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
+ { R200_RB3D_BLENDCOLOR, 3, "R200_RB3D_BLENDCOLOR" },
};
struct reg_names {
@@ -459,6 +463,7 @@ static struct reg_names reg_names[] = {
{ R200_PP_TXCBLEND2_7, "R200_PP_TXCBLEND2_7" },
{ R200_PP_TXABLEND_7, "R200_PP_TXABLEND_7" },
{ R200_PP_TXABLEND2_7, "R200_PP_TXABLEND2_7" },
+ { R200_RB3D_BLENDCOLOR, "R200_RB3D_BLENDCOLOR" },
{ R200_RB3D_ABLENDCNTL, "R200_RB3D_ABLENDCNTL" },
{ R200_RB3D_CBLENDCNTL, "R200_RB3D_CBLENDCNTL" },
{ R200_SE_TCL_OUTPUT_VTX_COMP_SEL, "R200_SE_TCL_OUTPUT_VTX_COMP_SEL" },
diff --git a/src/mesa/drivers/dri/radeon/radeon_sanity.c b/src/mesa/drivers/dri/radeon/radeon_sanity.c
index 11d0a33ce4a..4a6d7d1b2a9 100644
--- a/src/mesa/drivers/dri/radeon/radeon_sanity.c
+++ b/src/mesa/drivers/dri/radeon/radeon_sanity.c
@@ -138,6 +138,7 @@ static struct {
{ RADEON_PP_TEX_SIZE_0, 2, "RADEON_PP_TEX_SIZE_0" },
{ RADEON_PP_TEX_SIZE_1, 2, "RADEON_PP_TEX_SIZE_1" },
{ RADEON_PP_TEX_SIZE_2, 2, "RADEON_PP_TEX_SIZE_2" },
+ { 0, 3, "R200_RB3D_BLENDCOLOR" },
};
struct reg_names {