diff options
| author | Kenneth Graunke <[email protected]> | 2017-06-27 14:38:13 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2017-07-13 19:56:49 -0700 |
| commit | 24891d7c05b2b6bead540ad860af42fd1291826b (patch) | |
| tree | be70f6afb4916375ffb07e4fecb62a1a49bbbc5c /src/mesa | |
| parent | 6d28c6e52cfd76855c1368560dd90f12493e2580 (diff) | |
i965: Store per-stage push constant BO pointers.
Right now, we always upload new push constant data, and immediately
emit 3DSTATE_CONSTANT_* packets. We call intel_upload_space and store
the resulting BO pointer in brw->curbe.curbe_bo. We read that when
emitting the packets. This works today, but is fragile - it depends on
upload and packet emission being interleaved.
If we instead were to upload all the data, then emit all the packets,
then upload BO wrapping will get us into trouble. For example, the VS
constants may land in one upload BO, but the FS constants may not fit
and land in a second upload BO. Uploading FS constants would overwrite
the brw->curbe.curbe_bo pointer, so when we emitted 3DSTATE_CONSTANT_VS,
we'd get the wrong BO.
I intend to separate out this code in a future commit, so I need to fix
this. To fix it, we simply store a per-stage BO pointer.
Reviewed-by: Matt Turner <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_context.h | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen6_constant_state.c | 3 | ||||
| -rw-r--r-- | src/mesa/drivers/dri/i965/genX_state_upload.c | 3 |
3 files changed, 6 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_context.h b/src/mesa/drivers/dri/i965/brw_context.h index 3a613ff63e6..d7ea7fae31d 100644 --- a/src/mesa/drivers/dri/i965/brw_context.h +++ b/src/mesa/drivers/dri/i965/brw_context.h @@ -552,7 +552,8 @@ struct brw_stage_state /** Offset in the batchbuffer to Gen4-5 pipelined state (VS/WM/GS_STATE). */ uint32_t state_offset; - uint32_t push_const_offset; /* Offset in the batchbuffer */ + struct brw_bo *push_const_bo; /* NULL if using the batchbuffer */ + uint32_t push_const_offset; /* Offset in the push constant BO or batch */ int push_const_size; /* in 256-bit register increments */ /* Binding table: pointers to SURFACE_STATE entries. */ diff --git a/src/mesa/drivers/dri/i965/gen6_constant_state.c b/src/mesa/drivers/dri/i965/gen6_constant_state.c index f3927c5dba2..920f502ca37 100644 --- a/src/mesa/drivers/dri/i965/gen6_constant_state.c +++ b/src/mesa/drivers/dri/i965/gen6_constant_state.c @@ -65,7 +65,8 @@ gen6_upload_push_constants(struct brw_context *brw, const int size = prog_data->nr_params * sizeof(gl_constant_value); gl_constant_value *param; if (brw->gen >= 8 || brw->is_haswell) { - param = intel_upload_space(brw, size, 32, &brw->curbe.curbe_bo, + param = intel_upload_space(brw, size, 32, + &stage_state->push_const_bo, &stage_state->push_const_offset); } else { param = brw_state_batch(brw, size, 32, diff --git a/src/mesa/drivers/dri/i965/genX_state_upload.c b/src/mesa/drivers/dri/i965/genX_state_upload.c index b6678ec6941..e0b87b762d2 100644 --- a/src/mesa/drivers/dri/i965/genX_state_upload.c +++ b/src/mesa/drivers/dri/i965/genX_state_upload.c @@ -2858,7 +2858,8 @@ upload_constant_state(struct brw_context *brw, #if GEN_GEN >= 8 || GEN_IS_HASWELL pkt.ConstantBody.ReadLength[2] = stage_state->push_const_size; pkt.ConstantBody.Buffer[2] = - render_ro_bo(brw->curbe.curbe_bo, stage_state->push_const_offset); + render_ro_bo(stage_state->push_const_bo, + stage_state->push_const_offset); #else pkt.ConstantBody.ReadLength[0] = stage_state->push_const_size; pkt.ConstantBody.Buffer[0].offset = |