diff options
| author | Eric Anholt <[email protected]> | 2013-11-04 22:56:33 -0800 |
|---|---|---|
| committer | Eric Anholt <[email protected]> | 2013-11-12 15:05:07 -0800 |
| commit | 7c90947a0ba7f61b58a6fd5b94a08587e68d978e (patch) | |
| tree | 5178883aeb9b10e6608956e50cbc35360be6ea6e /src/mesa | |
| parent | bc0e3bb4d05fbb5e8e2af8dce8170cb78cfe0e70 (diff) | |
i965/fs: Fix message setup for SIMD8 spills.
In the SIMD16 spilling changes, I replaced a "1" in the spill path with
"mlen", but obviously it wasn't mlen before because spills have the g0
header along with the payload. The interface I was trying to use was
asking for how many physical regs we're writing, so we're looking for "1"
or "2".
I'm guessing this actually passed piglit because the high 8 bits of the
execution mask in SIMD8 mode are all 0s.
Cc: "10.0" <[email protected]>
Reviewed-by: Paul Berry <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_fs_generator.cpp | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp index 6678553ee25..cc58ff2598b 100644 --- a/src/mesa/drivers/dri/i965/brw_fs_generator.cpp +++ b/src/mesa/drivers/dri/i965/brw_fs_generator.cpp @@ -757,7 +757,7 @@ fs_generator::generate_scratch_write(fs_inst *inst, struct brw_reg src) retype(brw_message_reg(inst->base_mrf + 1), BRW_REGISTER_TYPE_UD), retype(src, BRW_REGISTER_TYPE_UD)); brw_oword_block_write_scratch(p, brw_message_reg(inst->base_mrf), - inst->mlen, inst->offset); + dispatch_width / 8, inst->offset); } void |