diff options
| author | Kenneth Graunke <[email protected]> | 2013-07-10 13:22:00 -0700 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-07-15 19:40:52 -0700 |
| commit | 43ea4342257d9d2c57eb379a6326258100c2156b (patch) | |
| tree | bfed3b39f4532627d5215ec26a24c34e8b713f26 /src/mesa | |
| parent | 3f64cfabfc0bae7f5dba9d541680edcc6b745cea (diff) | |
i965: Delete "the data cache is the sampler cache" comments on Gen7+.
I cut and pasted these comments from the Gen4 code during Ivybridge
enabling, and didn't understand what they meant at the time.
The data cache is NOT the same as the sampler cache on Ivybridge.
The sampler cache has L1 and L2 caches in addition to the L3 cache,
while data port messages to the "data cache" hit L3 directly.
This means that the sampler domain is technically wrong, but we stopped
caring about read/write domains quite a while ago. The kernel just
flushes all the caches at the end of each batchbuffer, and our render to
texture code flushes the sampler caches when necessary.
Signed-off-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 12 |
1 files changed, 0 insertions, 12 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 8c54152c014..684669ba723 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -259,10 +259,6 @@ gen7_update_buffer_texture_surface(struct gl_context *ctx, if (bo) { surf[1] = bo->offset; /* reloc */ - /* Emit relocation to surface contents. Section 5.1.1 of the gen4 - * bspec ("Data Cache") says that the data cache does not exist as - * a separate cache and is just the sampler cache. - */ drm_intel_bo_emit_reloc(brw->batch.bo, binding_table[surf_index] + 4, bo, 0, @@ -414,10 +410,6 @@ gen7_create_constant_surface(struct brw_context *brw, SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A); } - /* Emit relocation to surface contents. Section 5.1.1 of the gen4 - * bspec ("Data Cache") says that the data cache does not exist as - * a separate cache and is just the sampler cache. - */ drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4, bo, offset, @@ -454,10 +446,6 @@ gen7_create_shader_time_surface(struct brw_context *brw, uint32_t *out_offset) * overrides. */ - /* Emit relocation to surface contents. Section 5.1.1 of the gen4 - * bspec ("Data Cache") says that the data cache does not exist as - * a separate cache and is just the sampler cache. - */ drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4, brw->shader_time.bo, 0, |