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authorKenneth Graunke <[email protected]>2013-04-10 13:46:10 -0700
committerKenneth Graunke <[email protected]>2013-04-10 16:54:31 -0700
commiteef3dff3fda76a9f42b8f788b720bf7c69a25584 (patch)
treec99016cc274057ead89f74fbc2e0a3055b662547 /src/mesa
parentba38ac062c5b8c80e4d33ee680b86cabbfa19095 (diff)
intel: Refactor code in intel_miptree_choose_tiling().
This reduces the nesting level slightly, and in my opinion, makes it a bit easier to follow. Signed-off-by: Kenneth Graunke <[email protected]> Reviewed-by: Chad Versace <[email protected]> Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/intel/intel_mipmap_tree.c10
1 files changed, 6 insertions, 4 deletions
diff --git a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
index df70ccab2bc..8fcdb46bcbb 100644
--- a/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/intel/intel_mipmap_tree.c
@@ -342,15 +342,17 @@ intel_miptree_choose_tiling(struct intel_context *intel,
base_format == GL_DEPTH_STENCIL_EXT))
return I915_TILING_Y;
- if (width0 >= 64) {
- if (ALIGN(mt->total_width * mt->cpp, 512) < 32768)
- return intel->gen >= 6 ? I915_TILING_Y : I915_TILING_X;
+ /* If the width is smaller than a tile, don't bother tiling. */
+ if (width0 < 64)
+ return I915_TILING_NONE;
+ if (ALIGN(mt->total_width * mt->cpp, 512) >= 32768) {
perf_debug("%dx%d miptree too large to blit, falling back to untiled",
mt->total_width, mt->total_height);
+ return I915_TILING_NONE;
}
- return I915_TILING_NONE;
+ return intel->gen >= 6 ? I915_TILING_Y : I915_TILING_X;
}
struct intel_mipmap_tree *