diff options
| author | Matt Turner <[email protected]> | 2014-05-17 15:54:05 -0700 |
|---|---|---|
| committer | Matt Turner <[email protected]> | 2014-05-26 13:58:58 -0700 |
| commit | 4c7bf8a704c7d9f05fde6c8653734532b24bddd7 (patch) | |
| tree | 191124e257ec670f844523d1af8a674ea76ebdc2 /src/mesa | |
| parent | 0d3f83f4ad5f66a3ad62f1ec0cdc5029487e92f3 (diff) | |
i965: Switch types D->UD when possible to allow compaction.
Number of compacted instructions: 827404 -> 833045 (0.68%)
Reviewed-by: Eric Anholt <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_eu_emit.c | 21 |
1 files changed, 21 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_eu_emit.c b/src/mesa/drivers/dri/i965/brw_eu_emit.c index f831413cd47..7448512a7b5 100644 --- a/src/mesa/drivers/dri/i965/brw_eu_emit.c +++ b/src/mesa/drivers/dri/i965/brw_eu_emit.c @@ -295,6 +295,16 @@ validate_reg(struct brw_instruction *insn, struct brw_reg reg) /* 10. Check destination issues. */ } +static bool +is_compactable_immediate(unsigned imm) +{ + /* We get the low 12 bits as-is. */ + imm &= ~0xfff; + + /* We get one bit replicated through the top 20 bits. */ + return imm == 0 || imm == 0xfffff000; +} + void brw_set_src0(struct brw_compile *p, struct brw_instruction *insn, struct brw_reg reg) @@ -373,6 +383,17 @@ brw_set_src0(struct brw_compile *p, struct brw_instruction *insn, insn->bits1.da1.src0_reg_type == BRW_HW_REG_TYPE_F) { insn->bits1.da1.src0_reg_type = BRW_HW_REG_IMM_TYPE_VF; } + + /* There are no mappings for dst:d | i:d, so if the immediate is suitable + * set the types to :UD so the instruction can be compacted. + */ + if (is_compactable_immediate(insn->bits3.ud) && + insn->header.destreg__conditionalmod == BRW_CONDITIONAL_NONE && + insn->bits1.da1.src0_reg_type == BRW_HW_REG_TYPE_D && + insn->bits1.da1.dest_reg_type == BRW_HW_REG_TYPE_D) { + insn->bits1.da1.src0_reg_type = BRW_HW_REG_TYPE_UD; + insn->bits1.da1.dest_reg_type = BRW_HW_REG_TYPE_UD; + } } else { |