i965: Drop #ifdef I915 code.

Reviewed-by: Kenneth Graunke <[email protected]>

10 files changed, 5 insertions, 166 deletions

diff --git a/src/mesa/drivers/dri/i965/intel_blit.c b/src/mesa/drivers/dri/i965/intel_blit.c
index da56f55c4df..fa8c44532e6 100644
--- a/src/mesa/drivers/dri/i965/intel_blit.c
+++ b/src/mesa/drivers/dri/i965/intel_blit.c
@@ -357,7 +357,6 @@ intelEmitCopyBlit(struct intel_context *intel,
       return false;
    }
 
-#ifndef I915
    if (dst_tiling != I915_TILING_NONE) {
       CMD |= XY_DST_TILED;
       dst_pitch /= 4;
@@ -366,7 +365,6 @@ intelEmitCopyBlit(struct intel_context *intel,
       CMD |= XY_SRC_TILED;
       src_pitch /= 4;
    }
-#endif
 
    if (dst_y2 <= dst_y || dst_x2 <= dst_x) {
       return true;
@@ -499,12 +497,10 @@ intelClearWithBlit(struct gl_context *ctx, GLbitfield mask)
 
       assert(region->tiling != I915_TILING_Y);
 
-#ifndef I915
       if (region->tiling != I915_TILING_NONE) {
 	 CMD |= XY_DST_TILED;
 	 pitch /= 4;
       }
-#endif
       BR13 |= pitch;
 
       if (is_depth_stencil) {
@@ -619,12 +615,10 @@ intelEmitImmediateColorExpandBlit(struct intel_context *intel,
    opcode = XY_SETUP_BLT_CMD;
    if (cpp == 4)
       opcode |= XY_BLT_WRITE_ALPHA | XY_BLT_WRITE_RGB;
-#ifndef I915
    if (dst_tiling != I915_TILING_NONE) {
       opcode |= XY_DST_TILED;
       dst_pitch /= 4;
    }
-#endif
 
    br13 = dst_pitch | (translate_raster_op(logic_op) << 16) | (1 << 29);
    br13 |= br13_for_cpp(cpp);
@@ -736,12 +730,10 @@ intel_miptree_set_alpha_to_one(struct intel_context *intel,
    CMD = XY_COLOR_BLT_CMD;
    CMD |= XY_BLT_WRITE_ALPHA;
 
-#ifndef I915
    if (region->tiling != I915_TILING_NONE) {
       CMD |= XY_DST_TILED;
       pitch /= 4;
    }
-#endif
    BR13 |= pitch;
 
    /* do space check before going any further */
diff --git a/src/mesa/drivers/dri/i965/intel_buffer_objects.c b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
index f568864f4b4..57ff60b1f19 100644
--- a/src/mesa/drivers/dri/i965/intel_buffer_objects.c
+++ b/src/mesa/drivers/dri/i965/intel_buffer_objects.c
@@ -39,9 +39,7 @@
 #include "intel_mipmap_tree.h"
 #include "intel_regions.h"
 
-#ifndef I915
 #include "brw_context.h"
-#endif
 
 static GLboolean
 intel_bufferobj_unmap(struct gl_context * ctx, struct gl_buffer_object *obj);
@@ -51,17 +49,14 @@ static void
 intel_bufferobj_alloc_buffer(struct intel_context *intel,
 			     struct intel_buffer_object *intel_obj)
 {
+   struct brw_context *brw = brw_context(&intel->ctx);
+
    intel_obj->buffer = drm_intel_bo_alloc(intel->bufmgr, "bufferobj",
 					  intel_obj->Base.Size, 64);
 
-#ifndef I915
    /* the buffer might be bound as a uniform buffer, need to update it
     */
-   {
-      struct brw_context *brw = brw_context(&intel->ctx);
-      brw->state.dirty.brw |= BRW_NEW_UNIFORM_BUFFER;
-   }
-#endif
+   brw->state.dirty.brw |= BRW_NEW_UNIFORM_BUFFER;
 }
 
 static void
@@ -136,9 +131,7 @@ intel_bufferobj_data(struct gl_context * ctx,
 
    /* Part of the ABI, but this function doesn't use it.
     */
-#ifndef I915
    (void) target;
-#endif
 
    intel_obj->Base.Size = size;
    intel_obj->Base.Usage = usage;
@@ -152,19 +145,6 @@ intel_bufferobj_data(struct gl_context * ctx,
    intel_obj->sys_buffer = NULL;
 
    if (size != 0) {
-#ifdef I915
-      /* On pre-965, stick VBOs in system memory, as we're always doing
-       * swtnl with their contents anyway.
-       */
-      if (target == GL_ARRAY_BUFFER || target == GL_ELEMENT_ARRAY_BUFFER) {
-	 intel_obj->sys_buffer = malloc(size);
-	 if (intel_obj->sys_buffer != NULL) {
-	    if (data != NULL)
-	       memcpy(intel_obj->sys_buffer, data, size);
-	    return true;
-	 }
-      }
-#endif
       intel_bufferobj_alloc_buffer(intel, intel_obj);
       if (!intel_obj->buffer)
          return false;
diff --git a/src/mesa/drivers/dri/i965/intel_buffers.h b/src/mesa/drivers/dri/i965/intel_buffers.h
index 4e3d13087fe..320ea3a3a26 100644
--- a/src/mesa/drivers/dri/i965/intel_buffers.h
+++ b/src/mesa/drivers/dri/i965/intel_buffers.h
@@ -49,8 +49,5 @@ intel_draw_buffer(struct gl_context * ctx)
 }
 
 extern void intelInitBufferFuncs(struct dd_function_table *functions);
-#ifdef I915
-void intelCalcViewport(struct gl_context * ctx);
-#endif
 
 #endif /* INTEL_BUFFERS_H */
diff --git a/src/mesa/drivers/dri/i965/intel_context.c b/src/mesa/drivers/dri/i965/intel_context.c
index 2a325cd8438..12fcb55acde 100644
--- a/src/mesa/drivers/dri/i965/intel_context.c
+++ b/src/mesa/drivers/dri/i965/intel_context.c
@@ -660,14 +660,6 @@ intelInitContext(struct intel_context *intel,
 
    intel->prim.primitive = ~0;
 
-   /* Force all software fallbacks */
-#ifdef I915
-   if (driQueryOptionb(&intel->optionCache, "no_rast")) {
-      fprintf(stderr, "disabling 3D rasterization\n");
-      intel->no_rast = 1;
-   }
-#endif
-
    if (driQueryOptionb(&intel->optionCache, "always_flush_batch")) {
       fprintf(stderr, "flushing batchbuffer before/after each draw call\n");
       intel->always_flush_batch = 1;
diff --git a/src/mesa/drivers/dri/i965/intel_fbo.c b/src/mesa/drivers/dri/i965/intel_fbo.c
index d16523bbbf6..bd5f70f8feb 100644
--- a/src/mesa/drivers/dri/i965/intel_fbo.c
+++ b/src/mesa/drivers/dri/i965/intel_fbo.c
@@ -48,9 +48,7 @@
 #include "intel_mipmap_tree.h"
 #include "intel_regions.h"
 #include "intel_tex.h"
-#ifndef I915
 #include "brw_context.h"
-#endif
 
 #define FILE_DEBUG_FLAG DEBUG_FBO
 
@@ -806,14 +804,12 @@ intel_blit_framebuffer(struct gl_context *ctx,
                        GLint dstX0, GLint dstY0, GLint dstX1, GLint dstY1,
                        GLbitfield mask, GLenum filter)
 {
-#ifndef I915
    mask = brw_blorp_framebuffer(intel_context(ctx),
                                 srcX0, srcY0, srcX1, srcY1,
                                 dstX0, dstY0, dstX1, dstY1,
                                 mask, filter);
    if (mask == 0x0)
       return;
-#endif
 
    /* Try using the BLT engine. */
    mask = intel_blit_framebuffer_with_blitter(ctx,
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 4cc2e5bc561..df097d52be8 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -38,9 +38,7 @@
 #include "intel_tex.h"
 #include "intel_blit.h"
 
-#ifndef I915
 #include "brw_blorp.h"
-#endif
 
 #include "main/enums.h"
 #include "main/formats.h"
@@ -203,10 +201,6 @@ bool
 intel_is_non_msrt_mcs_buffer_supported(struct intel_context *intel,
                                        struct intel_mipmap_tree *mt)
 {
-#ifdef I915
-   /* MCS is not supported on the i915 (pre-Gen4) driver */
-   return false;
-#else
    struct brw_context *brw = brw_context(&intel->ctx);
 
    /* MCS support does not exist prior to Gen7 */
@@ -238,7 +232,6 @@ intel_is_non_msrt_mcs_buffer_supported(struct intel_context *intel,
       return false;
 
    return true;
-#endif
 }
 
 
@@ -275,9 +268,7 @@ intel_miptree_create_layout(struct intel_context *intel,
    mt->logical_width0 = width0;
    mt->logical_height0 = height0;
    mt->logical_depth0 = depth0;
-#ifndef I915
    mt->mcs_state = INTEL_MCS_STATE_NONE;
-#endif
 
    /* The cpp is bytes per (1, blockheight)-sized block for compressed
     * textures.  This is why you'll see divides by blockheight all over
@@ -412,15 +403,7 @@ intel_miptree_create_layout(struct intel_context *intel,
    intel_get_texture_alignment_unit(intel, mt->format,
 				    &mt->align_w, &mt->align_h);
 
-#ifdef I915
-   (void) intel;
-   if (intel->is_945)
-      i945_miptree_layout(mt);
-   else
-      i915_miptree_layout(mt);
-#else
    brw_miptree_layout(intel, mt);
-#endif
 
    return mt;
 }
@@ -609,7 +592,6 @@ intel_miptree_create(struct intel_context *intel,
        return NULL;
    }
 
-#ifndef I915
    /* If this miptree is capable of supporting fast color clears, set
     * mcs_state appropriately to ensure that fast clears will occur.
     * Allocation of the MCS miptree will be deferred until the first fast
@@ -617,7 +599,6 @@ intel_miptree_create(struct intel_context *intel,
     */
    if (intel_is_non_msrt_mcs_buffer_supported(intel, mt))
       mt->mcs_state = INTEL_MCS_STATE_RESOLVED;
-#endif
 
    return mt;
 }
@@ -710,7 +691,6 @@ intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
       return NULL;
    singlesample_mt->region->name = region->name;
 
-#ifndef I915
    /* If this miptree is capable of supporting fast color clears, set
     * mcs_state appropriately to ensure that fast clears will occur.
     * Allocation of the MCS miptree will be deferred until the first fast
@@ -718,7 +698,6 @@ intel_miptree_create_for_dri2_buffer(struct intel_context *intel,
     */
    if (intel_is_non_msrt_mcs_buffer_supported(intel, singlesample_mt))
       singlesample_mt->mcs_state = INTEL_MCS_STATE_RESOLVED;
-#endif
 
    if (num_samples == 0)
       return singlesample_mt;
@@ -814,9 +793,7 @@ intel_miptree_release(struct intel_mipmap_tree **mt)
       intel_region_release(&((*mt)->region));
       intel_miptree_release(&(*mt)->stencil_mt);
       intel_miptree_release(&(*mt)->hiz_mt);
-#ifndef I915
       intel_miptree_release(&(*mt)->mcs_mt);
-#endif
       intel_miptree_release(&(*mt)->singlesample_mt);
       intel_resolve_map_clear(&(*mt)->hiz_map);
 
@@ -1158,9 +1135,6 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
                         GLuint num_samples)
 {
    assert(intel->gen >= 7); /* MCS only used on Gen7+ */
-#ifdef I915
-   return false;
-#else
    assert(mt->mcs_mt == NULL);
 
    /* Choose the correct format for the MCS buffer.  All that really matters
@@ -1219,7 +1193,6 @@ intel_miptree_alloc_mcs(struct intel_context *intel,
    intel_miptree_unmap_raw(intel, mt->mcs_mt);
 
    return mt->mcs_mt;
-#endif
 }
 
 
@@ -1227,10 +1200,6 @@ bool
 intel_miptree_alloc_non_msrt_mcs(struct intel_context *intel,
                                  struct intel_mipmap_tree *mt)
 {
-#ifdef I915
-   assert(!"MCS not supported on i915");
-   return false;
-#else
    assert(mt->mcs_mt == NULL);
 
    /* The format of the MCS buffer is opaque to the driver; all that matters
@@ -1266,7 +1235,6 @@ intel_miptree_alloc_non_msrt_mcs(struct intel_context *intel,
                                      INTEL_MIPTREE_TILING_Y);
 
    return mt->mcs_mt;
-#endif
 }
 
 
@@ -1477,9 +1445,6 @@ void
 intel_miptree_resolve_color(struct intel_context *intel,
                             struct intel_mipmap_tree *mt)
 {
-#ifdef I915
-   /* Fast color clear is not supported on the i915 (pre-Gen4) driver */
-#else
    switch (mt->mcs_state) {
    case INTEL_MCS_STATE_NONE:
    case INTEL_MCS_STATE_MSAA:
@@ -1491,7 +1456,6 @@ intel_miptree_resolve_color(struct intel_context *intel,
       brw_blorp_resolve_color(intel, mt);
       break;
    }
-#endif
 }
 
 
@@ -1508,11 +1472,6 @@ void
 intel_miptree_make_shareable(struct intel_context *intel,
                              struct intel_mipmap_tree *mt)
 {
-#ifdef I915
-   /* Nothing needs to be done for I915 */
-   (void) intel;
-   (void) mt;
-#else
    /* MCS buffers are also used for multisample buffers, but we can't resolve
     * away a multisample MCS buffer because it's an integral part of how the
     * pixel data is stored.  Fortunately this code path should never be
@@ -1525,7 +1484,6 @@ intel_miptree_make_shareable(struct intel_context *intel,
       intel_miptree_release(&mt->mcs_mt);
       mt->mcs_state = INTEL_MCS_STATE_NONE;
    }
-#endif
 }
 
 
@@ -1592,7 +1550,6 @@ intel_miptree_updownsample(struct intel_context *intel,
                            unsigned width,
                            unsigned height)
 {
-#ifndef I915
    int src_x0 = 0;
    int src_y0 = 0;
    int dst_x0 = 0;
@@ -1617,7 +1574,6 @@ intel_miptree_updownsample(struct intel_context *intel,
                               width, height,
                               false, false /*mirror x, y*/);
    }
-#endif /* I915 */
 }
 
 static void
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
index 6dab092c8f3..c51194a88f7 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.h
@@ -201,7 +201,6 @@ enum intel_msaa_layout
 };
 
 
-#ifndef I915
 /**
  * Enum for keeping track of the state of an MCS buffer associated with a
  * miptree.  This determines when fast clear related operations are needed.
@@ -266,7 +265,6 @@ enum intel_mcs_state
     */
    INTEL_MCS_STATE_CLEAR,
 };
-#endif
 
 struct intel_mipmap_tree
 {
@@ -441,7 +439,6 @@ struct intel_mipmap_tree
     */
    struct intel_mipmap_tree *stencil_mt;
 
-#ifndef I915
    /**
     * \brief MCS miptree.
     *
@@ -457,7 +454,6 @@ struct intel_mipmap_tree
     * MCS state for this buffer.
     */
    enum intel_mcs_state mcs_state;
-#endif
 
    /**
     * The SURFACE_STATE bits associated with the last fast color clear to this
@@ -704,18 +700,12 @@ intel_miptree_all_slices_resolve_depth(struct intel_context *intel,
 static inline void
 intel_miptree_used_for_rendering(struct intel_mipmap_tree *mt)
 {
-#ifdef I915
-   /* Nothing needs to be done for I915, since it doesn't support fast
-    * clear.
-    */
-#else
    /* If the buffer was previously in fast clear state, change it to
     * unresolved state, since it won't be guaranteed to be clear after
     * rendering occurs.
     */
    if (mt->mcs_state == INTEL_MCS_STATE_CLEAR)
       mt->mcs_state = INTEL_MCS_STATE_UNRESOLVED;
-#endif
 }
 
 void
@@ -766,20 +756,9 @@ intel_miptree_unmap(struct intel_context *intel,
 		    unsigned int level,
 		    unsigned int slice);
 
-#ifdef I915
-static inline void
-intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
-	       unsigned int level, unsigned int layer, enum gen6_hiz_op op)
-{
-   /* Stub on i915.  It would be nice if we didn't execute resolve code at all
-    * there.
-    */
-}
-#else
 void
 intel_hiz_exec(struct intel_context *intel, struct intel_mipmap_tree *mt,
 	       unsigned int level, unsigned int layer, enum gen6_hiz_op op);
-#endif
 
 #ifdef __cplusplus
 }
diff --git a/src/mesa/drivers/dri/i965/intel_screen.c b/src/mesa/drivers/dri/i965/intel_screen.c
index 34e0caa81ca..61972dfe461 100644
--- a/src/mesa/drivers/dri/i965/intel_screen.c
+++ b/src/mesa/drivers/dri/i965/intel_screen.c
@@ -94,9 +94,7 @@ const GLuint __driNConfigOptions = 14;
 #include "intel_tex.h"
 #include "intel_regions.h"
 
-#ifndef I915
 #include "brw_context.h"
-#endif
 
 #include "i915_drm.h"
 
@@ -908,32 +906,6 @@ intelDestroyBuffer(__DRIdrawable * driDrawPriv)
  * init-designated function to register chipids and createcontext
  * functions.
  */
-extern bool
-i830CreateContext(int api,
-                  const struct gl_config *mesaVis,
-		  __DRIcontext *driContextPriv,
-		  unsigned major_version,
-		  unsigned minor_version,
-		  unsigned *error,
-		  void *sharedContextPrivate);
-
-extern bool
-i915CreateContext(int api,
-		  const struct gl_config *mesaVis,
-		  __DRIcontext *driContextPriv,
-                  unsigned major_version,
-                  unsigned minor_version,
-                  unsigned *error,
-		  void *sharedContextPrivate);
-extern bool
-brwCreateContext(int api,
-	         const struct gl_config *mesaVis,
-	         __DRIcontext *driContextPriv,
-                 unsigned major_version,
-                 unsigned minor_version,
-                 uint32_t flags,
-                 unsigned *error,
-		 void *sharedContextPrivate);
 
 static GLboolean
 intelCreateContext(gl_api api,
@@ -947,26 +919,10 @@ intelCreateContext(gl_api api,
 {
    bool success = false;
 
-#ifdef I915
-   __DRIscreen *sPriv = driContextPriv->driScreenPriv;
-   struct intel_screen *intelScreen = sPriv->driverPrivate;
-
-   if (IS_9XX(intelScreen->deviceID)) {
-      success = i915CreateContext(api, mesaVis, driContextPriv,
-                                  major_version, minor_version, error,
-                                  sharedContextPrivate);
-   } else {
-      intelScreen->no_vbo = true;
-      success = i830CreateContext(api, mesaVis, driContextPriv,
-                                  major_version, minor_version, error,
-                                  sharedContextPrivate);
-   }
-#else
    success = brwCreateContext(api, mesaVis,
                               driContextPriv,
                               major_version, minor_version, flags,
                               error, sharedContextPrivate);
-#endif
 
    if (success)
       return true;
diff --git a/src/mesa/drivers/dri/i965/intel_tex_copy.c b/src/mesa/drivers/dri/i965/intel_tex_copy.c
index d018cece1cb..935cccb19a0 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_copy.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_copy.c
@@ -41,9 +41,7 @@
 #include "intel_fbo.h"
 #include "intel_tex.h"
 #include "intel_blit.h"
-#ifndef I915
 #include "brw_context.h"
-#endif
 
 #define FILE_DEBUG_FLAG DEBUG_TEXTURE
 
@@ -102,12 +100,10 @@ intelCopyTexSubImage(struct gl_context *ctx, GLuint dims,
 {
    struct intel_context *intel = intel_context(ctx);
 
-#ifndef I915
    /* Try BLORP first.  It can handle almost everything. */
    if (brw_blorp_copytexsubimage(intel, rb, texImage, slice, x, y,
                                  xoffset, yoffset, width, height))
       return;
-#endif
 
    /* Next, try the BLT engine. */
    if (intel_copy_texsubimage(intel,
diff --git a/src/mesa/drivers/dri/i965/intel_tex_image.c b/src/mesa/drivers/dri/i965/intel_tex_image.c
index b359c57145a..0d0c7f18b52 100644
--- a/src/mesa/drivers/dri/i965/intel_tex_image.c
+++ b/src/mesa/drivers/dri/i965/intel_tex_image.c
@@ -23,9 +23,7 @@
 #include "intel_blit.h"
 #include "intel_fbo.h"
 
-#ifndef I915
 #include "brw_context.h"
-#endif
 
 #define FILE_DEBUG_FLAG DEBUG_TEXTURE
 
@@ -244,10 +242,10 @@ intel_set_texture_image_region(struct gl_context *ctx,
                                GLuint tile_y)
 {
    struct intel_context *intel = intel_context(ctx);
+   struct brw_context *brw = brw_context(ctx);
    struct intel_texture_image *intel_image = intel_texture_image(image);
    struct gl_texture_object *texobj = image->TexObject;
    struct intel_texture_object *intel_texobj = intel_texture_object(texobj);
-   bool has_surface_tile_offset = false;
    uint32_t draw_x, draw_y;
 
    _mesa_init_teximage_fields(&intel->ctx, image,
@@ -269,15 +267,12 @@ intel_set_texture_image_region(struct gl_context *ctx,
    intel_image->mt->level[0].slice[0].y_offset = tile_y;
 
    intel_miptree_get_tile_offsets(intel_image->mt, 0, 0, &draw_x, &draw_y);
-#ifndef I915
-   has_surface_tile_offset = brw_context(ctx)->has_surface_tile_offset;
-#endif
 
    /* From "OES_EGL_image" error reporting. We report GL_INVALID_OPERATION
     * for EGL images from non-tile aligned sufaces in gen4 hw and earlier which has
     * trouble resolving back to destination image due to alignment issues.
     */
-   if (!has_surface_tile_offset &&
+   if (!brw->has_surface_tile_offset &&
        (draw_x != 0 || draw_y != 0)) {
       _mesa_error(ctx, GL_INVALID_OPERATION, __func__);
       intel_miptree_release(&intel_image->mt);