diff options
| author | Abdiel Janulgue <[email protected]> | 2013-09-20 13:56:52 +0300 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2013-09-21 12:53:13 -0700 |
| commit | 1266f01dc76fb58dbbc2df6c1c639c9373584393 (patch) | |
| tree | 0a6fbbcfe8a609a682e82890e5c260a2fdd48001 /src/mesa | |
| parent | 4f1ebb8ddd0294698601a8c4fc38f1e39bfd51f6 (diff) | |
i965/gen7.5: Fix missing Shader Channel Select entries on Haswell
Probably non-intentional, but the SURFACE_STATE setup refactoring
for buffer surfaces had missed the scs bits when creating constant
surface states.
Fixes broken GLB 2.5 on Haswell where the knight's textures are missing
Signed-off-by: Abdiel Janulgue <[email protected]>
Reviewed-by: Kenneth Graunke <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/gen7_wm_surface_state.c | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c index 6938b1abc96..7571cbfadb1 100644 --- a/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c +++ b/src/mesa/drivers/dri/i965/gen7_wm_surface_state.c @@ -249,6 +249,13 @@ gen7_emit_buffer_surface_state(struct brw_context *brw, surf[5] = SET_FIELD(mocs, GEN7_SURFACE_MOCS); + if (brw->is_haswell) { + surf[7] |= (SET_FIELD(HSW_SCS_RED, GEN7_SURFACE_SCS_R) | + SET_FIELD(HSW_SCS_GREEN, GEN7_SURFACE_SCS_G) | + SET_FIELD(HSW_SCS_BLUE, GEN7_SURFACE_SCS_B) | + SET_FIELD(HSW_SCS_ALPHA, GEN7_SURFACE_SCS_A)); + } + /* Emit relocation to surface contents */ if (bo) { drm_intel_bo_emit_reloc(brw->batch.bo, *out_offset + 4, |