diff options
| author | Kenneth Graunke <[email protected]> | 2016-01-11 12:25:12 -0800 |
|---|---|---|
| committer | Kenneth Graunke <[email protected]> | 2016-01-12 12:19:47 -0800 |
| commit | 9095847c254be2d55ab188232aa6b84555dbac4e (patch) | |
| tree | 9316667c6e3e744a4cae806b47311a967b537b05 /src/mesa | |
| parent | 56fc2986d554b93d16fa1151765a9987bc42e4da (diff) | |
i965: Mark TCS URB writes as having side effects.
This adds barrier dependencies around TCS_OPCODE_URB_WRITE, preventing
reads and writes from being incorrectly scheduled.
Fixes rendering in GFXBench 4.0's tessellation demo.
For some reason, we haven't ever listed URB writes as having
side-effects. This hasn't been a problem because in most stages, we
never read from the URB, and only write to each location once.
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=93526
Signed-off-by: Kenneth Graunke <[email protected]>
Reviewed-by: Chris Forbes <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/brw_shader.cpp | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/i965/brw_shader.cpp b/src/mesa/drivers/dri/i965/brw_shader.cpp index efc24f92f58..0ac3f4a30fc 100644 --- a/src/mesa/drivers/dri/i965/brw_shader.cpp +++ b/src/mesa/drivers/dri/i965/brw_shader.cpp @@ -1022,6 +1022,7 @@ backend_instruction::has_side_effects() const case SHADER_OPCODE_URB_WRITE_SIMD8_MASKED_PER_SLOT: case FS_OPCODE_FB_WRITE: case SHADER_OPCODE_BARRIER: + case TCS_OPCODE_URB_WRITE: case TCS_OPCODE_RELEASE_INPUT: return true; default: |