diff options
| author | Neil Roberts <[email protected]> | 2015-02-19 16:09:41 +0000 |
|---|---|---|
| committer | Neil Roberts <[email protected]> | 2015-02-25 13:19:34 +0000 |
| commit | 67e3302497e90a4602921b4ac4621e97df60f850 (patch) | |
| tree | 71e715ddad44e76e2e3c9e454f205670b5c30e63 /src/mesa | |
| parent | 6d164f65c5a794164d07bc66c1f8f87280514e8c (diff) | |
i965: Don't force x-tiling for 16-bpp formats on Gen>7
Sandybridge doesn't support y-tiling for surface formats with 16 or
more bpp. There was previously an override to explicitly allow this
for Gen7. However, this restriction is also removed in Gen8+ so we
should use y-tiling there too.
This is important to do for Skylake which doesn't support x-tiling for
3D surfaces.
Reviewed-by: Ben Widawsky <[email protected]>
Diffstat (limited to 'src/mesa')
| -rw-r--r-- | src/mesa/drivers/dri/i965/intel_mipmap_tree.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c index 0e3888f3fbb..e085841b48d 100644 --- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c +++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c @@ -515,10 +515,10 @@ intel_miptree_choose_tiling(struct brw_context *brw, /* From the Sandybridge PRM, Volume 1, Part 2, page 32: * "NOTE: 128BPE Format Color Buffer ( render target ) MUST be either TileX * or Linear." - * 128 bits per pixel translates to 16 bytes per pixel. This is necessary - * all the way back to 965, but is explicitly permitted on Gen7. + * 128 bits per pixel translates to 16 bytes per pixel. This is necessary + * all the way back to 965, but is permitted on Gen7+. */ - if (brw->gen != 7 && mt->cpp >= 16) + if (brw->gen < 7 && mt->cpp >= 16) return I915_TILING_X; /* From the Ivy Bridge PRM, Vol4 Part1 2.12.2.1 (SURFACE_STATE for most |