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authorCorbin Simpson <[email protected]>2008-05-15 00:49:32 -0700
committerCorbin Simpson <[email protected]>2008-05-17 07:12:37 -0700
commit405ee871c54d78e63cef1a570578a755250102c8 (patch)
tree1a9d13e1378f3a00284f589aecf1b851fcfc32ff /src/mesa
parent0de02f1716edc16257339af78f198072da87539f (diff)
r5xx: Adding more opcodes.
EX2, FRC, LG2, SIN, RCP, and RSQ, if you care. All of these except FRC are like COS. This pretty much rounds out the set of opcodes which can be done in one ALU inst.
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/r300/r500_fragprog.c82
1 files changed, 82 insertions, 0 deletions
diff --git a/src/mesa/drivers/dri/r300/r500_fragprog.c b/src/mesa/drivers/dri/r300/r500_fragprog.c
index 0aa6dc474a6..550cc0dbdd8 100644
--- a/src/mesa/drivers/dri/r300/r500_fragprog.c
+++ b/src/mesa/drivers/dri/r300/r500_fragprog.c
@@ -497,6 +497,47 @@ static GLboolean parse_program(struct r500_fragment_program *fp)
fp->inst[counter].inst5 = R500_ALU_RGBA_OP_DP4
| R500_ALU_RGBA_ADDRD(dest);
break;
+ case OPCODE_EX2:
+ src[0] = make_src(fp, fpi->SrcReg[0]);
+ fp->inst[counter].inst0 = R500_INST_TYPE_ALU
+ | R500_INST_TEX_SEM_WAIT | pixel_mask;
+ fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
+ fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
+ fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
+ | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst4 = R500_ALPHA_OP_EX2
+ | R500_ALPHA_ADDRD(dest)
+ | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
+ | R500_ALU_RGBA_ADDRD(dest);
+ break;
+ case OPCODE_FRC:
+ src[0] = make_src(fp, fpi->SrcReg[0]);
+ fp->inst[counter].inst0 = R500_INST_TYPE_ALU
+ | R500_INST_TEX_SEM_WAIT | pixel_mask;
+ fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
+ fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
+ fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
+ | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst4 = R500_ALPHA_OP_FRC
+ | R500_ALPHA_ADDRD(dest)
+ | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst5 = R500_ALU_RGBA_OP_FRC
+ | R500_ALU_RGBA_ADDRD(dest);
+ case OPCODE_LG2:
+ src[0] = make_src(fp, fpi->SrcReg[0]);
+ fp->inst[counter].inst0 = R500_INST_TYPE_ALU
+ | R500_INST_TEX_SEM_WAIT | pixel_mask;
+ fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
+ fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
+ fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
+ | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst4 = R500_ALPHA_OP_LN2
+ | R500_ALPHA_ADDRD(dest)
+ | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
+ | R500_ALU_RGBA_ADDRD(dest);
+ break;
case OPCODE_MAD:
src[0] = make_src(fp, fpi->SrcReg[0]);
src[1] = make_src(fp, fpi->SrcReg[1]);
@@ -583,6 +624,47 @@ static GLboolean parse_program(struct r500_fragment_program *fp)
// | R500_ALU_RGBA_ALPHA_SEL_C_SRC2
| MAKE_SWIZ_ALPHA_C(R500_SWIZZLE_ZERO);
break;
+ case OPCODE_RCP:
+ src[0] = make_src(fp, fpi->SrcReg[0]);
+ fp->inst[counter].inst0 = R500_INST_TYPE_ALU
+ | R500_INST_TEX_SEM_WAIT | pixel_mask;
+ fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
+ fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
+ fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
+ | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst4 = R500_ALPHA_OP_RCP
+ | R500_ALPHA_ADDRD(dest)
+ | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
+ | R500_ALU_RGBA_ADDRD(dest);
+ break;
+ case OPCODE_RSQ:
+ src[0] = make_src(fp, fpi->SrcReg[0]);
+ fp->inst[counter].inst0 = R500_INST_TYPE_ALU
+ | R500_INST_TEX_SEM_WAIT | pixel_mask;
+ fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
+ fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
+ fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
+ | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst4 = R500_ALPHA_OP_RSQ
+ | R500_ALPHA_ADDRD(dest)
+ | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
+ | R500_ALU_RGBA_ADDRD(dest);
+ break;
+ case OPCODE_SIN:
+ src[0] = make_src(fp, fpi->SrcReg[0]);
+ fp->inst[counter].inst0 = R500_INST_TYPE_ALU
+ | R500_INST_TEX_SEM_WAIT | pixel_mask;
+ fp->inst[counter].inst1 = R500_RGB_ADDR0(src[0]);
+ fp->inst[counter].inst2 = R500_ALPHA_ADDR0(src[0]);
+ fp->inst[counter].inst3 = R500_ALU_RGB_SEL_A_SRC0
+ | MAKE_SWIZ_RGB_A(make_rgb_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst4 = R500_ALPHA_OP_SIN
+ | R500_ALPHA_ADDRD(dest)
+ | R500_ALPHA_SEL_A_SRC0 | MAKE_SWIZ_ALPHA_A(make_alpha_swizzle(fpi->SrcReg[0]));
+ fp->inst[counter].inst5 = R500_ALU_RGBA_OP_SOP
+ | R500_ALU_RGBA_ADDRD(dest);
case OPCODE_SUB:
src[0] = make_src(fp, fpi->SrcReg[0]);
src[1] = make_src(fp, fpi->SrcReg[1]);