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authorIago Toral Quiroga <[email protected]>2017-09-15 09:13:07 +0200
committerIago Toral Quiroga <[email protected]>2017-09-18 10:47:51 +0200
commit3d9cb39fd0c5895bd9774413e03c95c5b40bf030 (patch)
tree679ac5fb05ccfc8dec60b6b105a7510f44012ae0 /src/mesa
parent9a8bf42308f437c3895a5bc82024de33713d3cb6 (diff)
i965: emit BRW_NEW_AUX_STATE on aux state changes
Fixes a regression introduced with b96313c0e1289b296d7, which removed BRW_NEW_BLORP for a bunch of SURFACE_STATE setup code, including render targets, on the basis that blorp invalidates binding tables but not surface states, however, at least on Broadwell, this caused a regression in a CTS test, which Ken and Jason tracked down to the fact that we are not uploading new render target surface states after allocating new CCS_D surfaces for fast clears (which allocation is deferred until an actual clear occurs). The reason this only fails in BDW is that on SKL+ we use CCS_E which is allocated up front so it exists in the initial surface state, the problem can be reproduced in these platforms too if we use INTEL_DEBUG=norcb to force the CCS_D path. This patch, together with the ones preceding it, fixes the regression by ensuring that we track and flag as dirty all aux state changes. Credit goes to Jason and Ken for figuring out the reason for the regression. Fixes: KHR-GL45.transform_feedback.draw_xfb_test Reviewed-by: Jason Ekstrand <[email protected]>
Diffstat (limited to 'src/mesa')
-rw-r--r--src/mesa/drivers/dri/i965/intel_mipmap_tree.c8
1 files changed, 6 insertions, 2 deletions
diff --git a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
index 970eca723f8..253d3a13f9d 100644
--- a/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
+++ b/src/mesa/drivers/dri/i965/intel_mipmap_tree.c
@@ -2551,8 +2551,12 @@ intel_miptree_set_aux_state(struct brw_context *brw,
assert(intel_miptree_level_has_hiz(mt, level));
}
- for (unsigned a = 0; a < num_layers; a++)
- mt->aux_state[level][start_layer + a] = aux_state;
+ for (unsigned a = 0; a < num_layers; a++) {
+ if (mt->aux_state[level][start_layer + a] != aux_state) {
+ mt->aux_state[level][start_layer + a] = aux_state;
+ brw->ctx.NewDriverState |= BRW_NEW_AUX_STATE;
+ }
+ }
}
/* On Gen9 color buffers may be compressed by the hardware (lossless